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CN-121999841-A - Memory device and method of operating the same

CN121999841ACN 121999841 ACN121999841 ACN 121999841ACN-121999841-A

Abstract

The present disclosure provides a memory device and a method of operating the same. The method of operation includes the steps of receiving a writer mode instruction to operate the memory device for data loading and programming side-by-side operations through the system control logic, receiving and writing a plurality of word data to the memory buffer through the system control logic during data loading of the data loading and programming side-by-side operations, and reading the word data from the memory buffer and programming the word data to the memory array during data programming of the data loading and programming side-by-side operations, wherein the data programming period is partially overlapping with the data loading period. The memory device and the operation method thereof can effectively reduce the programming time of the system code.

Inventors

  • CHEN YUMING
  • LIN JISHUN

Assignees

  • 华邦电子股份有限公司

Dates

Publication Date
20260508
Application Date
20251031
Priority Date
20241103

Claims (20)

  1. 1. A method of operating a memory device, comprising: receiving a writer mode instruction to operate the memory device for data loading and programming parallel operations through system control logic; Receiving and writing a plurality of word data into a memory buffer by said system control logic during a data loading of said data loading and programming parallel operation, and The plurality of word data is read from the memory buffer and programmed to a memory array during a data programming period of the data loading and programming parallel operation, wherein the data programming period is partially overlapping with the data loading period.
  2. 2. The method of operation of claim 1, wherein there is a data write clock delay between a start time of the data loading period and a start time of the data programming period.
  3. 3. The method of claim 2, wherein the data write clock delay is related to a correction codeword length.
  4. 4. The method of operation of claim 1, wherein the plurality of word data includes N word data, and when the system control logic receives and writes second word data to the memory buffer at a current word cycle, reads first word data of a previous word cycle from the memory buffer and programs the first word data to the memory array.
  5. 5. The method of operation of claim 4, wherein reading and programming of the (N-1) th word data buffered by the memory buffer into the memory array is initiated when the system control logic completes receiving and writing the N-th word data to the memory buffer.
  6. 6. The method of operation of claim 5 wherein said memory buffer reads out and programs said nth word data from said memory buffer into said memory array after said data loading period.
  7. 7. The method of operation of claim 1, further comprising: Receiving a chip selection signal through a system control logic; Wherein when the level of the chip select signal switches from a first level to a second level, the system control logic begins to receive the writer mode instruction, Wherein the system control logic is to complete receiving and writing the plurality of word data to the memory buffer when the level of the chip select signal is switched from the second level to the first level.
  8. 8. The method of operation of claim 1, further comprising: A start programming address is received by the system control logic to program the plurality of word data read from the memory buffer into the memory array according to the start programming address.
  9. 9. The method of operation of claim 1, wherein the step of receiving and writing the plurality of word data to the memory buffer by the system control logic comprises: Generating a load word address to the memory buffer by an address counter, such that the memory device writes the plurality of word data to the memory buffer according to the load word address.
  10. 10. The method of operation of claim 1, wherein the step of programming the plurality of word data to the memory array comprises: Generating a programming word address to the memory buffer by an address counter to program the plurality of word data read out from the memory buffer to the memory array according to the programming word address.
  11. 11. The method of operation of claim 10, wherein the step of programming the plurality of word data to the memory array further comprises: Providing the programming word address to a word line decoder and a bit line decoder by the address counter, and The plurality of word data is programmed into a plurality of memory cells of the memory array by the word line decoder and the bit line decoder.
  12. 12. The method of operation of claim 1, further comprising: generating a load word address and a program word address for the memory buffer by an address counter; allocating one of a first word buffer and a second word buffer of the memory buffer by the memory device according to the load word address for receiving and writing the plurality of word data from the system control logic, and The plurality of word data in the other of the first word buffer and the second word buffer of the memory buffer allocated according to the programming word address by the memory device is read out to be programmed to the memory array.
  13. 13. The method of claim 12, wherein the address counter comprises a plurality of flip-flops, and wherein a data output and an inverted data output of one of the plurality of flip-flops are used to output the load word address and the program word address.
  14. 14. The method of operation of claim 1, wherein when reading the plurality of word data from the memory buffer, the system control logic generates corresponding check bits from the plurality of word data and programs the plurality of word data and the corresponding check bits to the memory array.
  15. 15. The method of operation of claim 1, wherein a programming bias voltage used during the data programming is different from a normal programming bias voltage.
  16. 16. The method of operation of claim 15, wherein a programming bias voltage used during the data programming is greater than a normal programming bias voltage.
  17. 17. The method of operation of claim 1, wherein the plurality of word data comprises system code.
  18. 18. The method of operation of claim 17 wherein the system code is a boot code.
  19. 19. The method of operation of claim 1, wherein the system control logic receives the plurality of word data via a serial peripheral interface or a fast channel interconnect interface.
  20. 20. A memory device, comprising: A memory array; A memory buffer coupled to the memory array, and System control logic coupled to the memory buffer and configured to receive writer mode instructions to operate the memory device for data loading and programming parallel operations, Wherein during a data load of the data load and program side-by-side operation, the system control logic receives and writes a plurality of word data to the memory buffer, Wherein the plurality of word data is read out from the memory buffer and programmed to the memory array during a data programming period of the data loading and programming parallel operation, and the data programming period is partially overlapped with the data loading period.

Description

Memory device and method of operating the same Technical Field The present disclosure relates to a memory device, and more particularly, to a memory device that performs system code programming and operation thereof. Background In general, conventional memory devices employ page programming instructions when executing system code (system code) programming. According to the page programming instruction, the system code must be completely written into the memory buffer, so that the chip selection signal changes its level in response to the system code, and then the system code is programmed into the memory cell according to the system code completely written into the memory buffer. That is, when the system code is one page in size, the system code of one page needs to be completely written into the memory buffer before starting programming the system code into the memory cells. That is, conventional memory devices need to wait until the system code is completely written into the memory buffer before programming the system code into the memory cells. Therefore, the time required to perform system code programming (hereinafter referred to as "required programming time") will be limited. In particular, if the system code is long, the programming time required is also long, and the memory buffer required is also large, so that it is disadvantageous in terms of both the operation efficiency and the miniaturization. Disclosure of Invention The present disclosure provides a memory device and an operating method thereof to solve the above-mentioned problems. The method of operating a memory device of the present disclosure includes receiving a writer mode instruction to operate the memory device for a data load and program side-by-side operation through system control logic, receiving and writing a plurality of word data to a memory buffer through the system control logic during a data load period of the data load and program side-by-side operation, and reading the plurality of word data from the memory buffer and programming the plurality of word data to a memory array during a data program period of the data load and program side-by-side operation, wherein the data program period is partially overlapping with the data load period. The memory device of the present disclosure includes a memory array, a memory buffer, and system control logic. The memory buffer is coupled to the memory array. The system control logic is coupled to the memory buffer and is configured to receive writer mode instructions to operate the memory device for data loading and programming parallel operations. During data loading of a parallel operation of data loading and programming, system control logic receives and writes a plurality of word data to a memory buffer. During data programming of a data loading and programming parallel operation, a plurality of word data is read out from the memory buffer and programmed to the memory array, and the data programming period is partially overlapped with the data loading period. Based on the above, according to the memory device and the operating method thereof of the present disclosure, the memory device can effectively reduce the time for programming the system code, and can also be advantageous for miniaturization. Drawings FIG. 1 is a schematic diagram of a memory device according to an embodiment of the disclosure; FIG. 2 is a flow chart of a method of operating a memory device according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram of a memory device according to another embodiment of the present disclosure; FIG. 4 is a schematic diagram of related signals of the embodiment of FIG. 3 according to the present disclosure; FIG. 5 is a schematic diagram of a plurality of flip-flops according to another embodiment of the present disclosure. Description of the reference numerals 100. 300 A memory device; A writer mode instruction; 102_1 to 102_N, 102_1 'to 102_N': word data; 110. system control logic 310; A memory cell 120; 130. memory buffer 330; 311, chip select pins; 312 clock input pins; 313 serial data input pins; 320 a memory array; 322 word line decoder; 323 bit line decoder; 340. 500, an address counter; 501-520, flip-flops; an is loading word address; Ab [ n ]: programming word address; WD, WD': word data; CSb, chip select signal; CLK is a clock signal; SI: serial data signal; SPA is the initial programming address; S210-S230, namely, a step of performing a process; t0 to t8 are time; PP: during data programming; PW, during data loading; WMC: writer mode instruction; DB_1 to DB_256, data bit groups; RST: reset signal; A0 to A19 are counter signals; ab 0-Ab 19, an inverse counter signal; A data input end; q is the data output end; qb, an inverted data output terminal; And R is a reset end. Detailed Description Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.