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CN-121999842-A - Method for operating memory device

CN121999842ACN 121999842 ACN121999842 ACN 121999842ACN-121999842-A

Abstract

The present disclosure provides a method of operating a memory device. A memory device to be operated includes a 0 th word line to an M th word line, a plurality of memory cells connected to a block of the memory device. The method of operation includes programming the block from the 0 th word line to the M th word line in N1 program-erase cycles, and programming the block from the M th word line to the 0 th word line in N2 program-erase cycles, where N1 and N2 are positive integers.

Inventors

  • LI SHIJUN
  • QIN QIYUAN

Assignees

  • 旺宏电子股份有限公司

Dates

Publication Date
20260508
Application Date
20241206
Priority Date
20241108

Claims (19)

  1. 1. A method of operating a memory device for a memory device, the memory device including a 0 th word line to an M-th word line, a plurality of memory cells connected to a block of the memory device, the method of operating the memory device comprising: Programming the block from the 0 th word line to the M th word line in N1 program-erase cycles, and Programming the block from the mth word line to the 0 th word line in N2 program-erase cycles; wherein N1 and N2 are positive integers.
  2. 2. The method of operation of a memory device of claim 1, wherein the memory device is an enterprise-level solid state disk.
  3. 3. The method of operation of a memory device of claim 1, comprising: A controller of the memory device is used to switch the programming sequence of the block between the step of programming the block from the 0 th word line to the M th word line in N1 program-erase cycles and the step of programming the block from the M th word line to the 0 th word line in N2 program-erase cycles.
  4. 4. The method of claim 3, wherein the frequency of switching is part of a firmware of the controller.
  5. 5. The method of claim 4, wherein the firmware includes two sets of opcodes for programming sequence from the 0 th word line to the M th word line and programming sequence from the M th word line to the 0 th word line, respectively.
  6. 6. The method of operation of a memory device of claim 1, further comprising: Recording a cycle number during N1 program-erase cycles in a controller of the memory device during the step of programming the block from the 0 th word line to the M th word line in N1 program-erase cycles, and a cycle number during N2 program-erase cycles in the controller during the step of programming the block from the M th word line to the 0 th word line in N2 program-erase cycles, and When the number of cycles during the N1 program-erase cycles or the number of cycles during the N2 program-erase cycles reaches a predetermined switching number of cycles, the programming sequence of the block is switched between from the 0 th word line to the M-th word line and from the M-th word line to the 0 th word line.
  7. 7. The method of operation of a memory device of claim 6, comprising: the steps of programming the block from the 0 th word line to the M th word line in the N1 program-erase cycles and programming the block from the M th word line to the 0 th word line in the N2 program-erase cycles are alternately repeated.
  8. 8. The method of operation of a memory device of claim 6, wherein N2 is equal to N1.
  9. 9. The method of operation of a memory device of claim 8, wherein N1 is 1000 to 1500 and N2 is 1000 to 1500.
  10. 10. The method of operation of a memory device of claim 1, comprising: When the number of cycles during the N1 program-erase cycles reaches a predetermined threshold, the programming sequence of the block is switched from the 0 th word line to the M-th word line to the 0 th word line.
  11. 11. The method of claim 1, wherein N1 is greater than or equal to N2, and the method of operating the memory device further comprises: after the step of programming the block from the mth word line to the 0 th word line in N2 program-erase cycles, the block from the 0 th word line to the mth word line is programmed in N3 program-erase cycles, N3 being equal to N2.
  12. 12. The method of operation of a memory device of claim 11, comprising: the steps of programming the block from the mth word line to the 0 th word line in N2 program-erase cycles and programming the block from the 0 th word line to the mth word line in N3 program-erase cycles are alternately repeated.
  13. 13. The method of operation of a memory device of claim 11, wherein N1 is 1000 to 2000, N2 is 500 to 1000, and N3 is 500 to 1000.
  14. 14. The method of operation of a memory device of claim 1, further comprising: monitoring the difference between the number of errors of a first group of word lines on the 0 th word line side and the number of errors of a second group of word lines on the M th word line side, and When the difference is greater than a switching threshold, the programming sequence of the block is switched between from the 0 th word line to the M th word line and from the M th word line to the 0 th word line.
  15. 15. The method of claim 14, wherein the first set of word lines includes the 0 th word line through a 4 th word line and the second set of word lines includes an M-4 th word line through the M-th word line.
  16. 16. The method of operation of a memory device of claim 14, comprising: The steps of programming the block from the 0 th word line to the M-th word line in N1 program-erase cycles and programming the block from the M-th word line to the 0 th word line in N2 program-erase cycles are alternately repeated.
  17. 17. The method of claim 14, wherein the monitoring is triggered after a predetermined number of trigger cycles.
  18. 18. The method of operation of a memory device of claim 17, wherein the predetermined number of trigger cycles in the step of programming the block from the mth word line to the 0 th word line in N2 program-erase cycles is less than the predetermined number of trigger cycles in the step of programming the block from the 0 th word line to the mth word line in N1 program-erase cycles.
  19. 19. The method of claim 17, wherein the predetermined number of trigger cycles in the step of programming the block from the 0 th word line to the M-th word line in N1 program-erase cycles is 1000 and the predetermined number of trigger cycles in the step of programming the block from the M-th word line to the 0 th word line in N2 program-erase cycles is 500.

Description

Method for operating memory device Technical Field The present disclosure relates to methods of operating memory devices. The present disclosure relates in particular to methods of operation involving programming blocks of memory devices in different programming sequences (program sequences). Background The reliability of the memory device is better when the memory cells of the NAND memory device stay in the programmed state longer before the memory cells are erased and new data is reprogrammed. Conversely, when the memory cell is in the erased state for a long time before programming, the reliability of the memory cell may be degraded. That is, it is better to keep the blocks of the memory device in the programmed state than in the erased state. Thus, to maintain reliability, a block of a NAND product is erased only before new data is allocated to the block. However, in some products, such as enterprise-level solid state disks (ENTERPRISE SSD, ESSD), open blocks are often present. Typically, the memory cells in a block are programmed in a programming sequence starting from word line 0. As such, in an open block, memory cells controlled by a code smaller word line may have been programmed before the block is fully programmed and turned off, while memory cells controlled by a code larger word line may remain in the erased state for a longer period of time, for example, about one hour. Therefore, the memory cells controlled by the word lines with larger codes experience more serious degradation than the memory cells controlled by the word lines with smaller codes due to longer time in the erased state, creating a problem of reliability imbalance within the block. The problem of reliability imbalance becomes more pronounced over multiple program-erase cycles. Disclosure of Invention The present disclosure provides a method of operating a memory device to address the above-described reliability imbalance problem. A memory device to be operated includes a 0 th word line to an M th word line, a plurality of memory cells connected to a block of the memory device. The method of operation according to the present disclosure includes programming the block from the 0 th word line to the M th word line in N1 program-erase cycles, and programming the block from the M th word line to the 0 th word line in N2 program-erase cycles, where N1 and N2 are positive integers. Drawings For a better understanding of the above and other aspects of the disclosure, reference is made to the following detailed description of embodiments, which is to be taken in conjunction with the accompanying drawings. Fig. 1 is a flow chart of a method of operation of a memory device according to the present disclosure. FIG. 2 is a schematic diagram of one example of a memory device to be operated. Fig. 3 is a schematic diagram of one example of a method of operation according to the present disclosure. Fig. 4 is a schematic diagram of another example of a method of operation according to the present disclosure. Fig. 5 is a schematic diagram of yet another example of an operating method according to the present disclosure. Reference numerals illustrate: 100 memory device 200 Block 300 Controller 400 Word line driver 500 Bit line driver 600 Signal line BL (0): bit line/0 th bit line BL (1) bit line/1 st bit line BL (2) bit line/2 nd bit line BL (3) bit line/3 rd bit line BL (4) bit line/4 th bit line BL (M-4) bit line/Mth-4 bit line BL (M-3) bit line/Mth-3 bit line BL (M-2) bit line/Mth-2 bit line BL (M-1): bit line/Mth-1 bit line BL (M) bit line/Mth bit line GBL global bit line M: memory cell WL (0) word line/0 th word line WL (1) word line/1 st word line WL (2) word line/2 nd word line WL (3) word line/3 rd word line WL (4) word line/4 th word line WL (M-4) word line/Mth-4 word line WL (M-3) word line/Mth-3 word line WL (M-2) word line/Mth-2 word line WL (M-1) word line/Mth-1 word line WL (M) word line/Mth word line S1, step S2, step T1 period of time T2 time point T3 time period T4, time point. Detailed Description Various embodiments are described in greater detail below in conjunction with the accompanying drawings. The description and drawings are provided for purposes of illustration only and are not intended to be limiting. For purposes of clarity, the components may not be shown in actual scale. Moreover, some components and/or symbols may be omitted in certain drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. In the present disclosure, a method of operating a memory device is provided. Fig. 1 is a flow chart of a method of operation of a memory device according to the present disclosure. FIG. 2 is a schematic diagram of one example of a memory device 100 to be operated. Memory device 100 may be a NAND memory device, such as an enterprise-level solid state disk (eSSD), which typically has an open block. The memory device 100 includes a0