CN-121999847-A - Memory, operation method thereof, trimming register and memory system

Abstract

The embodiment of the disclosure discloses a memory, an operation method thereof, a trimming register, a memory system and electronic equipment. The memory comprises a precharge circuit, a trimming register and a read output circuit, wherein the precharge circuit is configured to precharge a read node based on a precharge signal, the trimming register is coupled with the read node, the trimming register is configured to output trimming information latched in the trimming register based on a read enable signal and select whether to discharge the read node based on the trimming information, the read output circuit is coupled with the read node, and the read output circuit is configured to generate a read output signal based on the read output enable signal and the level of the read node, wherein the read output signal is used for indicating whether the trimming information is correct.

Inventors

• ZHANG SIMIN
• MEI XIAODONG
• ZHANG HUANGPENG
• FU XIANG
• HU CHUNYAN

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260508

Application Date

20241107

Claims (20)

1. 1. A memory, comprising: A precharge circuit configured to precharge the read node based on a precharge signal; A trimming register coupled to the read node, the trimming register configured to output trimming information latched in the trimming register based on a read enable signal and to select whether to discharge the read node based on the trimming information; And a read output circuit coupled to the read node, the read output circuit configured to generate a read output signal based on a read output enable signal and a level of the read node, wherein the read output signal is used to indicate whether the trimming information is correct.
2. 2. The memory of claim 1, wherein the trimming register comprises: a dynamic latch circuit configured to latch the trimming information; An output circuit coupled to the dynamic latch circuit, the output circuit configured to: outputting the trimming information latched by the dynamic latch circuit based on the reading enabling signal; and discharging the read node in response to the trimming information being output in the first state.
3. 3. The memory of claim 2, wherein the precharge circuit is specifically configured to precharge the read node to a first level based on the precharge signal; the output circuit is specifically configured to discharge the read node from the first level to a second level based on the trimming information being output in the first state; The read output circuit is specifically configured to generate a first read output signal based on the read node being at the second level and the read output enable signal, wherein the first read output signal is used to indicate whether the trimming information in the first state is correct.
4. 4. The memory of claim 2, wherein the output circuit is further configured to: And in response to the trimming information being output in a second state, maintaining the level of the read node, wherein the second state is different from the first state.
5. 5. The memory of claim 4, wherein the precharge circuit is specifically configured to precharge the read node to a first level based on the precharge signal; The read output circuit is specifically configured to generate a second read output signal based on the read node being at the first level and the read output enable signal, wherein the second read output signal is used to indicate whether the trimming information in the second state is correct.
6. 6. The memory of claim 2, wherein the output circuit comprises a first transistor and a second transistor, wherein a first terminal of the first transistor is coupled to a first power supply terminal, a second terminal of the first transistor is coupled to a first terminal of the second transistor, a control terminal of the first transistor is configured to receive the read enable signal, a second terminal of the second transistor is coupled to the read node, and a control terminal of the second transistor is configured to receive the trimming information.
7. 7. The memory of claim 6, wherein the trimming register further comprises an address selection circuit comprising at least one third transistor, wherein a first terminal of the third transistor is coupled to the dynamic latch circuit, a second terminal of the third transistor is coupled to the first power supply terminal, a control terminal of the third transistor is configured to receive an address signal, and a first terminal of the first transistor is coupled to the first power supply terminal through the third transistor.
8. 8. The memory of claim 1, wherein the memory further comprises: A plurality of the trimming registers are used for trimming the memory cells, a plurality of trimming registers are commonly coupled to the read node; The input end of the latch circuit is coupled with the read output circuit, the output end of the latch circuit is coupled with a pin, and the latch circuit is configured to: and carrying out latch processing on the read output data in the read output signal, wherein the read output data is used for indicating whether the trimming information latched in the corresponding trimming register is correct or not.
9. 9. The memory of claim 1, wherein the memory further comprises: Control logic circuitry coupled to the precharge circuitry, the trimming register, and the read output circuitry, respectively, the control logic circuitry configured to: Generating the precharge signal at a first time; And generating the reading enabling signal at a second moment after the first moment.
10. 10. The memory of claim 1, wherein the precharge circuit comprises a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the read node, a second terminal of the fourth transistor is coupled to a second power supply terminal, and a control terminal of the fourth transistor is configured to receive the precharge signal.
11. 11. A method of operating a memory, comprising: Precharging the read node based on the precharge signal; Outputting trimming information latched in the trimming register based on the reading enabling signal; discharging the read node in response to the trimming information being output in a first state, wherein the trimming register is coupled to the read node; And generating a first read output signal based on the read node discharging to a second level and a read output enable signal, wherein the first read output signal is used for indicating whether the trimming information in the first state is correct.
12. 12. The method of operation of claim 11, wherein the precharging the read node based on the precharge signal comprises: pre-charging the read node to a first level based on the pre-charge signal, wherein the first level is greater than the second level; the discharging the read node in response to the trimming information being output in a first state, comprising: In response to the trimming information being output in the first state, discharging the read node from the first level to the second level.
13. 13. The method of operation of claim 11, further comprising: and in response to the trimming information being output in a second state, maintaining the read node at a first level, wherein the second state and the first state are different, and the first level is greater than the second level.
14. 14. The method of operation of claim 13, further comprising: And generating a second read output signal based on the read node being at the first level and the read output enable signal, wherein the second read output signal is used for indicating whether the trimming information in the second state is correct.
15. 15. The method of operation of claim 14, wherein the precharging the read node based on the precharge signal comprises: The read node is precharged to the first level based on the precharge signal.
16. 16. The method of operation of claim 14, wherein the memory includes a plurality of trimming registers, the plurality of trimming registers being commonly coupled to the read node, the method of operation further comprising: And carrying out latch processing on read output data in the first read output signal or the second read output signal, wherein the read output data are respectively used for indicating whether the trimming information latched in the corresponding trimming register is correct or not.
17. 17. A trimming register, which comprises a trimming register, characterized by comprising the following steps: A dynamic latch circuit configured to latch trimming information; An output circuit coupled to the dynamic latch circuit, the output circuit configured to: Outputting the trimming information latched by the dynamic latch circuit based on a reading enabling signal; and responsive to the trimming information being output in the first state, discharging the read node from the first level to the second level.
18. 18. The trimming register of claim 17, wherein the output circuit is further configured to: and in response to the trimming information being output in a second state, maintaining a read node at the first level.
19. 19. The trimming register of claim 17, wherein the output circuit comprises a first transistor and a second transistor, wherein a first terminal of the first transistor is coupled to a first power supply terminal, a second terminal of the first transistor is coupled to a first terminal of the second transistor, a control terminal of the first transistor is configured to receive the read enable signal, a second terminal of the second transistor is coupled to the read node, and a control terminal of the second transistor is configured to receive the trimming information.
20. 20. The trimming register of claim 19, further comprising an address selection circuit comprising at least one third transistor, wherein a first terminal of the third transistor is coupled to the dynamic latch circuit, a second terminal of the third transistor is coupled to the first power supply terminal, a control terminal of the third transistor is configured to receive an address signal, and a first terminal of the first transistor is coupled to the first power supply terminal through the third transistor.

Description

Memory, operation method thereof, trimming register and memory system Technical Field The embodiment of the disclosure relates to the technical field of memories, and relates to a memory, an operation method thereof, a trimming register, a memory system and electronic equipment. Background The Memory is classified into a volatile Memory and a nonvolatile Memory according to whether or not stored data is reserved at power-off, wherein the volatile Memory in which data is lost at power-off may include a Static Random-Access Memory (SRAM) and a dynamic Random-Access Memory (Dynamic Random Access Memory, DRAM). After the memory is manufactured, the influence of process deviation, layout error and the like on the memory can be adjusted through a trim (trim) test, so that the memory performance is improved. For example, the memory may adjust the operating parameters of the memory by accessing trimming information registered in a trimming register. Disclosure of Invention According to a first aspect of embodiments of the present disclosure, there is provided a memory including a precharge circuit configured to precharge a read node based on a precharge signal, a trimming register coupled to the read node, the trimming register configured to output trimming information latched in the trimming register based on a read enable signal and to select whether to discharge the read node based on the trimming information, and a read output circuit coupled to the read node, the read output circuit configured to generate a read output signal based on a read output enable signal and a level of the read node, wherein the read output signal is used to indicate whether the trimming information is correct. In some embodiments, the trimming register includes a dynamic latch circuit configured to latch the trimming information and an output circuit coupled to the dynamic latch circuit, the output circuit configured to output the trimming information latched by the dynamic latch circuit based on the read enable signal, and to discharge the read node in response to the trimming information being output in a first state. In some embodiments, the precharge circuit is specifically configured to precharge the read node to a first level based on the precharge signal, the output circuit is specifically configured to discharge the read node from the first level to a second level based on the trimming information being output in the first state, and the read output circuit is specifically configured to generate a first read output signal based on the read node being in the second level and the read output enable signal, wherein the first read output signal is used to indicate whether the trimming information being in the first state is correct. In some embodiments, the output circuit is further configured to maintain the level of the read node in response to the trimming information being output in a second state, wherein the second state is different from the first state. In some embodiments, the precharge circuit is specifically configured to precharge the read node to a first level based on the precharge signal, and the read output circuit is specifically configured to generate a second read output signal based on the read node being at the first level and the read output enable signal, wherein the second read output signal is used to indicate whether the trimming information in the second state is correct. In some embodiments, the output circuit comprises a first transistor and a second transistor, wherein a first end of the first transistor is coupled to a first power supply end, a second end of the first transistor is coupled to a first end of the second transistor, a control end of the first transistor is configured to receive the read enable signal, a second end of the second transistor is coupled to the read node, and a control end of the second transistor is configured to receive the trimming information. In some embodiments, the trimming register further comprises an address selection circuit comprising at least one third transistor, wherein a first end of the third transistor is coupled to the dynamic latch circuit, a second end of the third transistor is coupled to the first power supply end, a control end of the third transistor is configured to receive an address signal, and a first end of the first transistor is coupled to the first power supply end through the third transistor. In some embodiments, the memory further comprises a plurality of trimming registers and a latch circuit, wherein the trimming registers are commonly coupled to the read node, an input end of the latch circuit is coupled to the read output circuit, an output end of the latch circuit is coupled to a pin, and the latch circuit is configured to latch read output data in the read output signal, wherein the read output data is used for indicating whether the trimming information latched in the corresponding trimming register is correct or not. In some embodi