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CN-121999849-A - Method and system for testing solid state disk based on PCIE SWITCH chips

CN121999849ACN 121999849 ACN121999849 ACN 121999849ACN-121999849-A

Abstract

The invention discloses a solid state disk testing method and system based on PCIE SWITCH chips, and relates to the technical field of solid state disk testing, wherein an uplink PCIe port of a testing host is expanded into a plurality of independent downlink PCIe ports through at least one PCIE SWITCH chip so as to be connected with a plurality of solid state disks; dynamically configuring the port connection relation to form a flexibly reconfigurable logic topology, independently controlling the corresponding solid state disk to enter or exit a specified low-power consumption state by operating an independent control interface mapped to a target downlink port, and responding to the connection state change under the condition that the system is not powered off to complete the identification and configuration of the newly accessed solid state disk. The method breaks through the limitation of a single machine test scale through hardware expansion, realizes flexible scheduling of test resources through dynamic topology reconstruction, realizes single-disk-level accurate power consumption control through an independent interface, and ensures continuity and automation of a test flow through hot plug support.

Inventors

  • Luo Diewen

Assignees

  • 东莞记忆存储科技有限公司

Dates

Publication Date
20260508
Application Date
20260122

Claims (10)

  1. 1. A solid state disk testing method based on PCIE SWITCH chips is characterized by comprising the following steps: Expanding an uplink PCIe port of the test host into a plurality of independent downlink PCIe ports through at least one PCIE SWITCH chip, wherein each downlink PCIe port is used for being connected with a solid state disk; Dynamically configuring the port connection relation of the at least one PCIE SWITCH chip to form a flexibly reconfigurable logic topology between the uplink PCIe port and the plurality of downlink PCIe ports; independently controlling a solid state disk connected to a target downlink PCIe port to enter or exit a specified low-power consumption state by operating an independent control interface mapped to the target downlink PCIe port; Under the condition that the system is not powered off, the identification and configuration of the newly-accessed solid state disk are completed in response to the change of the connection state of the solid state disk on any downlink PCIe port.
  2. 2. The method for testing a solid state disk based on PCIE SWITCH chips as defined in claim 1, wherein the expanding, by at least one PCIE SWITCH chip, the upstream PCIe port of the test host to a plurality of independent downstream PCIe ports includes: Providing an expansion board card integrated with a plurality PCIE SWITCH chips; connecting a PCIe link provided by the test host to the expansion board card; and expanding the accessed PCIe links into a plurality of independent downlink PCIe ports for connecting the solid state disk through each PCIE SWITCH chip.
  3. 3. The method for testing a solid state disk based on PCIE SWITCH chips as defined in claim 1, wherein dynamically configuring the port connection relationship of the at least one PCIE SWITCH chip includes: Performing bandwidth aggregation configuration on an uplink PCIe port of the PCIE SWITCH chip; And/or programmable logic binding or isolating the specific downstream PCIe port from the specific upstream PCIe port.
  4. 4. The method for testing a solid state disk based on PCIE SWITCH chips according to claim 1, wherein the independently controlling the solid state disk connected to the target downstream PCIe port to enter or exit from the specified low power consumption state by operating an independent control interface mapped to the target downstream PCIe port includes: And triggering a PCIe link connected with the target downstream PCIe port to switch to or recover from the specified low power consumption state by controlling the level of a specific electrical signal associated with the target downstream PCIe port.
  5. 5. The method for testing a solid state disk based on PCIE SWITCH chips as defined in claim 1, wherein the step of completing the identification and configuration of the newly-accessed solid state disk in response to the change of the connection state of the solid state disk on any one of the downstream PCIe ports includes: maintaining independent identification information for each downlink PCIe port; When a connection event of the downlink PCIe port is detected, the corresponding downlink PCIe port is positioned according to the identification information, and initialization operation is performed on the newly accessed solid state disk.
  6. 6. The PCIE SWITCH chip-based solid state disk testing method as claimed in claim 1, further comprising: based on the flexible reconfiguration logic topology, a test instruction is issued to a plurality of downlink PCIe ports through the uplink PCIe ports to execute parallel test on the connected plurality of solid state disks.
  7. 7. A solid state disk testing system for performing the method of any of claims 1-6, comprising: testing a host; an expansion hardware unit comprising at least one PCIE SWITCH chip, wherein the PCIE SWITCH chip is provided with an uplink PCIe port for connecting the test host and a plurality of downlink PCIe ports for expanding connection; The hard disk connectors are respectively and electrically connected to a plurality of downlink PCIe ports of the expansion hardware unit and are used for installing the solid state disk; The expansion hardware unit is configured to support dynamic configuration of connection relations between an uplink PCIe port and a downlink PCIe port, provide an independent power consumption state control mechanism for at least one downlink PCIe port, and support hot plug event management of a solid state disk connected to the downlink PCIe port.
  8. 8. The system of claim 7, wherein the expansion hardware unit is a printed circuit board with a plurality of the PCIE SWITCH chips integrated thereon.
  9. 9. The system of claim 7, wherein the independent power consumption state control mechanism is implemented by configuring a universal input output pin of the PCIE SWITCH chip as a control signal source and mapping the control signal to a designated downstream PCIe port to control power consumption state switching of a PCIe link where the downstream PCIe port is located.
  10. 10. The system of claim 7, wherein the expansion hardware unit is configured to maintain separate identification information for each downstream PCIe port and to be able to report event notifications based on the identification information when hot plug events occur on a connected solid state disk.

Description

Method and system for testing solid state disk based on PCIE SWITCH chips Technical Field The invention relates to the technical field of solid state disk testing, in particular to a solid state disk testing method, device, computer equipment and storage medium based on PCIE SWITCH chips. Background In the field of testing of NVMe solid state disks, currently, a standard PC motherboard is generally directly used to connect to a solid state disk to be tested for testing. The above scheme relies on the native PCIe lanes provided by the motherboard itself, connecting the limited m.2 slots directly to the CPU or chipset, forming a point-to-point fixed link without any switching or expanding chips. The method has the following defects: firstly, the number of solid state disks which can be connected simultaneously by a single test host is limited due to the physical design of the main board, the test throughput is severely restricted, and large-scale concurrent test cannot be realized. Furthermore, in the scene of needing to verify the low-power consumption characteristic of the solid state disk, the conventional method generally sets the global power consumption state through a system layer, and cannot control and measure the independent and accurate deep low-power consumption state of any single hard disk, so that the test granularity is rough. Furthermore, the hard disk is replaced in the testing process and is required to be plugged and unplugged physically after power failure, the process is complicated, the testing continuity is interrupted, the degree of automation is low, and the overall testing efficiency is affected. Disclosure of Invention The embodiment of the invention provides a solid state disk testing method, a solid state disk testing device, computer equipment and a storage medium based on PCIE SWITCH chips, and aims to solve the technical problem of providing an NVMe solid state disk testing scheme which can support parallel testing of large-scale solid state disks, realize single-equipment fine-granularity power consumption control and has high-efficiency automatic rotation capability. In a first aspect, an embodiment of the present invention provides a method for testing a solid state disk based on PCIE SWITCH chips, including: Expanding an uplink PCIe port of the test host into a plurality of independent downlink PCIe ports through at least one PCIE SWITCH chip, wherein each downlink PCIe port is used for being connected with a solid state disk; Dynamically configuring the port connection relation of the at least one PCIE SWITCH chip to form a flexibly reconfigurable logic topology between the uplink PCIe port and the plurality of downlink PCIe ports; independently controlling a solid state disk connected to a target downlink PCIe port to enter or exit a specified low-power consumption state by operating an independent control interface mapped to the target downlink PCIe port; Under the condition that the system is not powered off, the identification and configuration of the newly-accessed solid state disk are completed in response to the change of the connection state of the solid state disk on any downlink PCIe port. Optionally, the expanding, by at least one PCIE SWITCH chip, the upstream PCIe port of the test host to a plurality of independent downstream PCIe ports includes: Providing an expansion board card integrated with a plurality PCIE SWITCH chips; connecting a PCIe link provided by the test host to the expansion board card; and expanding the accessed PCIe links into a plurality of independent downlink PCIe ports for connecting the solid state disk through each PCIE SWITCH chip. Optionally, the dynamically configuring the port connection relationship of the at least one PCIE SWITCH chip includes: Performing bandwidth aggregation configuration on an uplink PCIe port of the PCIE SWITCH chip; And/or programmable logic binding or isolating the specific downstream PCIe port from the specific upstream PCIe port. Optionally, the independently controlling the solid state hard disk connected to the target downstream PCIe port to enter or exit from the specified low power consumption state by operating an independent control interface mapped to the target downstream PCIe port includes: And triggering a PCIe link connected with the target downstream PCIe port to switch to or recover from the specified low power consumption state by controlling the level of a specific electrical signal associated with the target downstream PCIe port. Optionally, the responding to the connection state change of the solid state disk on any one of the downstream PCIe ports completes identification and configuration of the newly-accessed solid state disk, including: maintaining independent identification information for each downlink PCIe port; When a connection event of the downlink PCIe port is detected, the corresponding downlink PCIe port is positioned according to the identification information, and initializ