CN-121999850-A - Memory device with built-in self-test

Abstract

A memory device is disclosed. The memory device includes a single-pass programming cell array, a physically unclonable function cell array, and a controller. The single-time programming unit array comprises a plurality of single-time programming units. The physically unclonable function unit array includes a plurality of physically unclonable function units. The controller performs a first read operation on the physically unclonable function cell array to read a plurality of first bit values, performs a second read operation on the physically unclonable function cell array to read a plurality of second bit values after the first read operation, performs a comparison operation on the first bit values and the second bit values, and determines whether to allow a single program load operation to read the single program cell array according to a result of the comparison operation.

Inventors

• SHAO QIYI
• Wu Jiache

Assignees

• 熵码科技股份有限公司

Dates

Publication Date

20260508

Application Date

20251103

Priority Date

20241104

Claims (20)

1. 1. A memory device, comprising: an array of One-time Programmable (OTP) cells comprising a plurality of One-time programming cells; an array of physically unclonable function (Physical Unclonable Function, PUF) cells comprising a plurality of physically unclonable function cells, an The controller is configured to perform a first read operation on the physical unclonable function cell array to read a plurality of first bit values, perform a second read operation on the physical unclonable function cell array to read a plurality of second bit values after the first read operation, perform a comparison operation on the first bit values and the second bit values, and determine whether to allow a single program-load operation to read the single program cell array based at least on a result of the comparison operation.
2. 2. The memory device of claim 1, wherein: each two of the physical uncloneable function units are configured as a pair and have complementary bit values according to their physical characteristics, and The first bit values include bit values of a plurality of first physically unclonable function units in the physically unclonable function units, and the second bit values include bit values of a plurality of second physically unclonable function units in the physically unclonable function units paired with the first physically unclonable function units.
3. 3. The memory device of claim 2, wherein the controller determines to allow the single program load operation when the result of the comparison indicates that each of the first physically uncloneable function units has a bit value that is different from a bit value of a second physically uncloneable function unit of the second physically uncloneable function units that is paired with the first physically uncloneable function unit.
4. 4. The memory device of claim 2, wherein: When the result of the comparison indicates that a first physically unclonable function unit of the first physically unclonable function units has a bit value identical to a bit value of a second physically unclonable function unit of the second physically unclonable function units paired with the first physically unclonable function unit, the controller determines to perform a failure handling operation, Wherein the fault handling operation includes at least one of sending an alert and disabling the single program load operation.
5. 5. The memory device of claim 2, wherein the controller determines to perform a registration operation on the physically uncloneable function units when the result of the comparison indicates that the first bit values and the second bit values are all the same.
6. 6. The memory device of claim 1, wherein: The first read operation is performed by reading the first bit values from at least some of the physically unclonable function units, and the second read operation is performed by reading the second bit values from the at least some of the physically unclonable function units again.
7. 7. The memory device of claim 6, wherein the bit values of the physically unclonable function units are uncorrelated with each other.
8. 8. The memory device of claim 6, wherein: The physical unclonable function units comprise a plurality of first physical unclonable function units and a plurality of second physical unclonable function units, wherein each of the first physical unclonable function units is paired with a second physical unclonable function unit in the second physical unclonable function units to have complementary bit values, and The first read operation and the second read operation are performed on the first physically uncloneable function units.
9. 9. The memory device of claim 6, wherein: When the result of the comparison operation indicates that the first bit values read by the first read operation are different from the second bit values read by the second read operation, the controller determines to execute the fault handling operation, and The fault handling operation includes at least one of sending an alert and disabling the single program load operation.
10. 10. The memory device of claim 6, wherein the controller is further configured to calculate hamming weights for the first bit values or the second bit values when the result of the comparison indicates that the first bit values read by the first read operation are the same as the second bit values read by the second read operation (HAMMING WEIGHT).
11. 11. The memory device of claim 10, wherein the controller determines to allow the single program load operation when the hamming weight is within a predetermined range.
12. 12. The memory device of claim 11, wherein the controller is further configured to perform a registration operation on the physically unclonable function units when the hamming weight is 0% or 100%, and to perform a fault handling operation when the hamming weight is not 0%, 100%, or within the predetermined range, wherein the fault handling operation includes at least one of sending an alert and disabling the single program load operation.
13. 13. A method for determining stability of a memory device, wherein the memory device comprises an array of one-time programmable (OTP) cells, and an array of Physically Uncloneable Function (PUF) cells, the array of one-time programmable cells comprising a plurality of one-time programmable cells, the array of physically uncloneable function cells comprising a plurality of physically uncloneable function cells, and the method comprising: Performing a first read operation on the array of physically unclonable function cells to read a plurality of first bit values; Performing a second read operation on the physically unclonable function cell array after the first read operation to read a plurality of second bit values; performing a comparison operation on the first bit values and the second bit values, and A determination is made as to whether a single program load operation is allowed to read the single program cell array based at least on the result of the comparison operation.
14. 14. The method of claim 13, wherein: Each two of the physically unclonable function units are arranged in a pair to have complementary bit values according to their physical characteristics, and The first bit values include bit values of a plurality of first physically unclonable function units in the physically unclonable function units, and the second bit values include bit values of a plurality of second physically unclonable function units in the physically unclonable function units paired with the first physically unclonable function units.
15. 15. The method of claim 14, wherein the step of determining whether to allow the one-time program load operation to read the one-time program cell array based at least on a result of the comparing operation comprises: when the result of the comparison indicates that each of the first physically unclonable function units has a bit value different from a bit value of a second physically unclonable function unit of the second physically unclonable function units paired with the first physically unclonable function unit, determining to allow the single program load operation.
16. 16. The method of claim 14, further comprising: Determining to perform a fault handling operation when a first physical uncloneable function of the first physical uncloneable function has a bit value that is the same as a bit value of a second physical uncloneable function of the second physical uncloneable function paired with the first physical uncloneable function; Wherein the fault handling operation includes at least one of sending an alert and disabling the single program load operation.
17. 17. The method of claim 14, further comprising: when the result of the comparison indicates that the first bit values and the second bit values are all the same, determining to execute registration operation on the physically unclonable function units.
18. 18. The method of claim 13, wherein: The first read operation is performed by reading the first bit values from at least some of the physically unclonable function units, and the second read operation is performed by reading the second bit values from the at least some of the physically unclonable function units again.
19. 19. The method of claim 18, further comprising: determining to perform a fault handling operation when the result of the comparing operation indicates that the first bit values read by the first reading operation are different from the second bit values read by the second reading operation, and Wherein the fault handling operation includes at least one of sending an alert and disabling the single program load operation.
20. 20. The method of claim 18, further comprising: when the result of the comparison operation indicates that the first bit values read by the first reading operation are identical to the second bit values read by the second reading operation, calculating the Hamming weights of the first bit values or the second bit values When the hamming weight is within a predetermined range, it is determined that the single program load operation is allowed.

Description

Memory device with built-in self-test Technical Field The present invention relates to a memory device, and more particularly, to a memory device with built-In Self-Test (BIST) function. Background Generally, when a System on Chip (SoC) is started, it follows a predefined start-up sequence. For example, when power is turned on, the single chip system performs basic hardware initialization and then reads configuration data, such as security keys, boot configuration, and hardware settings, from One-time programming (One-time Programmable) memory for system setup and verification. Then, the single chip System may further initialize a Central Processing Unit (CPU), execute a boot program from a Read-only Memory (ROM), and finally boot an Operating System (OS). However, at the initial stage of the single chip system start-up process, the system voltage may not have stabilized. This instability can lead to errors in reading data from the single program memory. Because the data stored in the single-pass memory may contain critical content (e.g., system security keys and configuration data), the identity verification and boot process of the single-chip system may fail if the data is not correctly read from the single-pass memory. Therefore, how to ensure the stability of the single-time programming memory before reading the data from the single-time programming memory has become an issue to be solved. Disclosure of Invention One aspect of the present disclosure provides a memory device. The memory device includes an array of one-time programmable (OTP) cells, an array of Physically Unclonable Function (PUF) cells, and a controller. The single-time programming unit array comprises a plurality of single-time programming units. The physically unclonable function unit array includes a plurality of physically unclonable function units. The controller performs a first read operation on the physically unclonable function cell array to read a plurality of first bit values, performs a second read operation on the physically unclonable function cell array to read a plurality of second bit values after the first read operation, performs a compare operation on the plurality of first bit values and the plurality of second bit values, and determines whether to allow a single program-load operation to read the single program cell array based at least on a result of the compare operation. Another aspect of the present disclosure provides a method for determining memory device stability. The memory device includes an array of single-pass programming cells, an array of physically unclonable function cells, and a controller. The single-time programming unit array comprises a plurality of single-time programming units, and the physical unclonable function unit array comprises a plurality of physical unclonable function units. The method for determining the stability of the memory device includes performing a first read operation on the physically unclonable function cell array to read a plurality of first bit values, performing a second read operation on the physically unclonable function cell array to read a plurality of second bit values after the first read operation, performing a compare operation on the plurality of first bit values and the plurality of second bit values, and determining whether to allow a single program-load operation to read the single program cell array based at least on a result of the compare operation. Drawings The invention may be more completely understood by reference to the detailed description and claims in connection with the accompanying drawings, in which like reference numerals refer to like elements throughout. FIG. 1 illustrates a single chip system (SoC) according to an embodiment of the present disclosure; FIG. 2 illustrates a memory device according to an embodiment of the present disclosure; FIG. 3 illustrates paired physically uncloneable function units according to one embodiment of the present disclosure; FIG. 4 illustrates a flowchart of a method for determining memory device stability in accordance with an embodiment of the present disclosure; FIG. 5 illustrates a flowchart of steps for performing a determination of whether to allow a single program load operation, in accordance with one embodiment of the present disclosure; FIG. 6 illustrates a memory device according to another embodiment of the present disclosure; FIG. 7 illustrates a flowchart of steps for performing a determination of whether to allow a single program load operation, according to another embodiment of the present disclosure. Detailed Description Fig. 1 illustrates a single chip system (SoC) 10 according to an embodiment of the present disclosure. The single chip system 10 is an integrated circuit that can integrate the various components of a computer or other electronic system onto a single chip. For example, the single chip system 10 may include a central processing unit (Central Processing Unit, CPU) 11, an on-di