Search

CN-121999851-A - Memory operation method, memory system and electronic equipment

CN121999851ACN 121999851 ACN121999851 ACN 121999851ACN-121999851-A

Abstract

The application discloses a memory operation method, a memory system and electronic equipment, and relates to the technical field of memory. The method includes controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter if a first type of instruction is received, and controlling a sensing process for the selected memory cell using a second type of control parameter if a second type of instruction is received. According to the method, the first type of control parameters or the second type of control parameters are selected to control the sensing process according to the received different instructions in the memory, so that two types of control parameters aiming at the sensing process are provided, and the sensing requirements of different scenes can be met.

Inventors

  • QI WEI
  • DONG ZHIPENG
  • ZHAO XIANGNAN
  • LI DA

Assignees

  • 长江存储科技有限责任公司

Dates

Publication Date
20260508
Application Date
20241107

Claims (16)

  1. 1. A method of operating a memory, the memory comprising a plurality of memory cells, the method comprising: Controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter upon receipt of a first type of instruction; controlling a sensing process for the selected memory cell using a second type of control parameter if a second type of instruction is received; The sensing process for the selected memory cell is used for detecting the state of the threshold voltage of the selected memory cell, and the first type of control parameter and the second type of control parameter are different.
  2. 2. The method of claim 1, wherein N memory cells of the plurality of memory cells are coupled to a selected bit line, the N memory cells including the selected memory cell and a non-selected memory cell, the non-selected memory cell coupled to a non-selected word line, the N being an integer greater than 1, the first type of control parameter comprising a first turn-on voltage, the second type of control parameter comprising a second turn-on voltage; The controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter includes: applying the first turn-on voltage to the non-selected word line during sensing for the selected memory cell; the controlling a sensing process for the selected memory cell using a second type of control parameter, comprising: Applying the second turn-on voltage to the non-selected word line during sensing for the selected memory cell; wherein the first turn-on voltage is less than the second turn-on voltage.
  3. 3. The method of claim 1, wherein the selected memory cell is coupled to a selected bit line, the first type of control parameter comprises a first discharge duration, and the second type of control parameter comprises a second discharge duration; The controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter includes: Determining, during sensing for the selected memory cell, a state in which a threshold voltage of the selected memory cell is located based on a voltage of a sensing node SO at a first end time; the controlling a sensing process for the selected memory cell using a second type of control parameter, comprising: determining, during sensing for the selected memory cell, a state in which a threshold voltage of the selected memory cell is located based on a voltage of the SO at a second end time; The interval between the first end time and the start time of the sensing process for the selected memory cell is the first discharge duration, the interval between the second end time and the start time of the sensing process for the selected memory cell is the second discharge duration, and the first discharge duration is less than the second discharge duration.
  4. 4. The method of claim 1, wherein the selected memory cell is coupled to a selected bit line, the first type of control parameter comprises a first bias voltage, and the second type of control parameter comprises a second bias voltage; The controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter includes: applying the first bias voltage to the selected bit line during sensing for the selected memory cell; the controlling a sensing process for the selected memory cell using a second type of control parameter, comprising: Applying the second bias voltage to the selected bit line during sensing for the selected memory cell; wherein the first bias voltage is less than the second bias voltage.
  5. 5. The method of any of claims 1-4, wherein the selected memory cell is coupled to a selected word line; The method further comprises the steps of: applying a first read voltage to the selected word line while controlling a sensing process for the selected memory cell using the first type of control parameter; in the case where the threshold voltage of the selected memory cell is less than the first read voltage, a program operation is performed on the selected memory cell to adjust the threshold voltage of the selected memory cell in an erased state.
  6. 6. The method of any of claims 1-4, wherein the selected memory cell is coupled to a selected word line; The method further comprises the steps of: Applying a second read voltage to the selected word line while controlling a sensing process for the selected memory cell using the first type of control parameter; Data is written to the selected memory cell if the threshold voltage of the selected memory cell is less than the second read voltage.
  7. 7. The method of any one of claims 1 to 4, wherein controlling a sensing process for the selected memory cell using a second type of control parameter comprises: controlling a sensing process for the selected memory cell using the second type of control parameter to read data stored by the selected memory cell; Or alternatively The second type of control parameter is used to control a sensing process for the selected memory cell to verify whether the selected memory cell is programmed to an intended memory state.
  8. 8. A memory, wherein the memory comprises a peripheral circuit and a memory cell array, the memory cell array comprising a plurality of memory cells; the peripheral circuitry is configured to: Controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter upon receipt of a first type of instruction; controlling a sensing process for the selected memory cell using a second type of control parameter if a second type of instruction is received; The sensing process for the selected memory cell is used for detecting the state of the threshold voltage of the selected memory cell, and the first type of control parameter and the second type of control parameter are different.
  9. 9. The memory of claim 8, wherein N memory cells of the plurality of memory cells are coupled to a selected bit line, the N memory cells including the selected memory cell and a non-selected memory cell, the non-selected memory cell coupled to a non-selected word line, the N being an integer greater than 1, the first type of control parameter including a first turn-on voltage, the second type of control parameter including a second turn-on voltage; The peripheral circuitry is further configured to: Applying the first turn-on voltage to the non-selected word line during sensing for the selected memory cell upon receipt of the first type of instruction; Applying the second turn-on voltage to the non-selected word line during sensing for the selected memory cell if the second type of instruction is received; wherein the first turn-on voltage is less than the second turn-on voltage.
  10. 10. The memory of claim 8, wherein the selected memory cell is coupled to a selected bit line, the first type of control parameter comprises a first discharge duration, and the second type of control parameter comprises a second discharge duration; The peripheral circuitry is further configured to: determining, in a sense process for the selected memory cell, a state in which a threshold voltage of the selected memory cell is located based on a voltage of a sense node SO at a first end time upon receipt of the first type of instruction; determining, in a sense process for the selected memory cell, a state in which a threshold voltage of the selected memory cell is based on a voltage of the SO at a second end time, upon receipt of the second type of instruction; The interval between the first end time and the start time of the sensing process for the selected memory cell is the first discharge duration, the interval between the second end time and the start time of the sensing process for the selected memory cell is the second discharge duration, and the first discharge duration is less than the second discharge duration.
  11. 11. The memory of claim 8, wherein the selected memory cell is coupled to a selected bit line, the first type of control parameter comprises a first bias voltage, and the second type of control parameter comprises a second bias voltage; The peripheral circuitry is further configured to: Applying the first bias voltage to the selected bit line during sensing for the selected memory cell upon receipt of the first type of instruction; Applying the second bias voltage to the selected bit line during sensing for the selected memory cell if the second type of instruction is received; wherein the first bias voltage is less than the second bias voltage.
  12. 12. The memory of any of claims 8 to 11, wherein the selected memory cell is coupled to a selected word line; The peripheral circuit is further configured to: applying a first read voltage to the selected word line while controlling a sensing process for the selected memory cell using the first type of control parameter; in the case where the threshold voltage of the selected memory cell is less than the first read voltage, a program operation is performed on the selected memory cell to adjust the threshold voltage of the selected memory cell in an erased state.
  13. 13. The memory of any of claims 8 to 11, wherein the selected memory cell is coupled to a selected word line; The peripheral circuit is further configured to: Applying a second read voltage to the selected word line while controlling a sensing process for the selected memory cell using the first type of control parameter; Data is written to the selected memory cell if the threshold voltage of the selected memory cell is less than the second read voltage.
  14. 14. The memory according to any one of claims 8 to 11, wherein, The peripheral circuitry is further configured to: Controlling a sensing process for the selected memory cell using the second type control parameter to read data stored by the selected memory cell if the second type instruction is received; Or alternatively Upon receiving the second type of instruction, the second type of control parameter is used to control a sensing process for the selected memory cell to verify whether the selected memory cell is programmed to an intended memory state.
  15. 15. A memory system comprising at least one memory including peripheral circuitry and an array of memory cells, the array of memory cells including a plurality of memory cells, the peripheral circuitry configured to implement the method of any of claims 1-7, and a controller coupled to the at least one memory to control the at least one memory to store data.
  16. 16. An electronic device comprising a host and a storage system coupled to the host, the storage system comprising at least one memory and a controller, the memory comprising peripheral circuitry and an array of memory cells, the array of memory cells comprising a plurality of memory cells, the peripheral circuitry configured to implement the method of any of claims 1-7, the controller coupled to the at least one memory to control the at least one memory to store data.

Description

Memory operation method, memory system and electronic equipment Technical Field The embodiment of the application relates to the technical field of storage, in particular to a memory operation method, a memory, a storage system and electronic equipment. Background In a memory, a sense (sense) process is used to detect a state of a threshold voltage of a memory cell, and specifically, whether the memory cell is turned on or not after a read voltage is applied to the memory cell reflects a magnitude relationship between the threshold voltage and the read voltage of the memory cell. There are various scenes in the memory where sensing needs to be performed, and how to reasonably control the sensing process to meet the sensing requirements of different scenes needs to be further studied. Disclosure of Invention The embodiment of the application provides a memory operation method, a memory system and electronic equipment. The technical scheme provided by the embodiment of the application is as follows: according to an aspect of an embodiment of the present application, there is provided a method of operating a memory including a plurality of memory cells, the method including: Controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter upon receipt of a first type of instruction; controlling a sensing process for the selected memory cell using a second type of control parameter if a second type of instruction is received; The sensing process for the selected memory cell is used for detecting the state of the threshold voltage of the selected memory cell, and the first type of control parameter and the second type of control parameter are different. According to an aspect of an embodiment of the present application, there is provided a memory including a peripheral circuit and a memory cell array including a plurality of memory cells; the peripheral circuitry is configured to: Controlling a sensing process for a selected memory cell of the plurality of memory cells using a first type of control parameter upon receipt of a first type of instruction; controlling a sensing process for the selected memory cell using a second type of control parameter if a second type of instruction is received; The sensing process for the selected memory cell is used for detecting the state of the threshold voltage of the selected memory cell, and the first type of control parameter and the second type of control parameter are different. According to an aspect of an embodiment of the present application, there is provided a memory system including at least one memory including a peripheral circuit and a memory cell array including a plurality of memory cells, the peripheral circuit configured to implement the method of operating the above memory, and a controller coupled to the at least one memory to control the at least one memory to store data. According to an aspect of an embodiment of the present application, there is provided an electronic device including a host and a storage system coupled to the host, the storage system including at least one memory including a peripheral circuit and a storage cell array including a plurality of storage cells, and a controller coupled to the at least one memory to control the at least one memory to store data, the peripheral circuit being configured to implement the method of operating the above memory. The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects: By selecting the first type of control parameters or the second type of control parameters to control the sensing process according to different received instructions in the memory, two types of control parameters aiming at the sensing process are provided, and the sensing requirements of different scenes can be met. Drawings FIG. 1 is a block diagram of an electronic device having a storage system provided in one embodiment of the application; FIG. 2 is a schematic diagram of a memory card according to one embodiment of the present application; FIG. 3 is a schematic diagram of a solid state drive provided by one embodiment of the present application; FIG. 4 is a schematic diagram of a memory cell array according to an embodiment of the present application; FIG. 5 is a flow chart of a method of operation of a memory provided by one embodiment of the application; FIG. 6 is a schematic diagram of the voltage application of the sensing process provided by one embodiment of the present application; FIG. 7 is a schematic diagram showing distribution of threshold voltages when different on-voltages are used in the sensing process according to one embodiment of the present application; FIG. 8 is a schematic diagram of a voltage change condition of a sensing node according to an embodiment of the present application; FIG. 9 is a schematic diagram showing the distribution of threshold voltages when the sensing proce