CN-121999853-A - Method and device for determining failure type of storage unit and computer equipment

CN121999853ACN 121999853 ACN121999853 ACN 121999853ACN-121999853-A

Abstract

The application relates to a method and a device for determining failure type of a storage unit and computer equipment. The method comprises the steps of obtaining test data corresponding to a failure storage unit in a memory, wherein the test data comprise logical addresses of the failure storage unit in the memory, mapping the logical addresses into physical addresses of the failure storage unit in a memory layout, classifying the failure storage unit according to a preset layout structure rule and the physical addresses, and determining failure types, wherein the layout structure rule comprises an association relation between a common physical structure of the memory layout and the physical addresses. By adopting the method, the failure classification errors of the storage unit can be reduced, and the accuracy of failure classification is improved.

Inventors

TIAN FENG
LIU PAN

Assignees

上海积塔半导体有限公司

Dates

Publication Date: 20260508
Application Date: 20260127

Claims (10)

1. A method for determining a failure type of a storage unit, the method comprising: Obtaining test data corresponding to a failure storage unit in a memory, wherein the test data comprises a logic address of the failure storage unit in the memory; Mapping the logical address into a physical address of the invalid storage unit in a memory layout; And classifying the failure storage units according to preset layout structure rules and the physical addresses to determine failure types, wherein the layout structure rules comprise association relations between common physical structures and physical addresses of a memory layout.
2. The method of claim 1, wherein the physical address comprises row and column coordinates, wherein the mapping the logical address to the physical coordinates of the failed memory cell in a memory layout comprises: converting the logical address into a physical block address, a memory block address, a segment address, a word line address, and a bit line address; Determining a storage area of the failure storage unit in a memory layout based on the physical block address, the storage block address and the segment address; the row coordinates of the failed memory cell within the memory region are determined based on the word line address, and the column coordinates of the failed memory cell within the memory region are determined based on the bit line address.
3. The method of claim 1, wherein the failure types include a first four-bit failure type and a second four-bit failure type, wherein the second four-bit failure type includes two-bit failure modes or four single-bit failure modes, wherein the physical address includes physical coordinates, wherein the physical coordinates include row coordinates and column coordinates, wherein the classifying the failed memory cells according to a preset layout structure rule and the physical address, and wherein determining the failure type includes: If the physical coordinates of the four failed storage units are detected to meet the matrix of 2 x 2, selecting one physical coordinate from the physical coordinates of the four failed storage units as a physical coordinate of a reference point; calculating the sum of row coordinates and column coordinates of the datum points, and judging whether the four storage units have a shared physical structure in the layout according to the parity of the sum; If the shared physical structure exists, judging that the four failure storage units belong to the first four-bit failure type; And if the shared physical structure does not exist, judging that the four failure storage units belong to the second four-bit failure type.
4. The method of claim 3, wherein the reference point is a failed memory cell whose physical coordinate is a lower right corner or a failed memory cell whose physical coordinate is an upper left corner, wherein the physical coordinate uses a word line address as a row coordinate and a bit line address as a column coordinate, wherein the common physical structure includes a contact hole, wherein the calculating a sum of the row coordinate and the column coordinate of the reference point, and wherein the determining whether the four memory cells have the common physical structure in the layout according to parity of the sum comprises one of: Calculating the sum of the row coordinates and the column coordinates of the failure storage unit with the physical coordinates of the lower right corner, wherein the contact holes are arranged under the condition that the sum is odd; and calculating the sum of the row coordinates and the column coordinates of the failure memory cell with the physical coordinates of the upper left corner, wherein the contact hole exists when the sum is odd, and the contact hole does not exist when the sum is even.
5. The method of claim 3, wherein the reference point is a failed memory cell with a physical coordinate of an upper right corner or a failed memory cell with a physical coordinate of a lower left corner, wherein the physical coordinate uses a word line address as a row coordinate and a bit line address as a column coordinate, wherein the common physical structure comprises a contact hole, wherein the calculating the sum of the row coordinate and the column coordinate of the reference point, and wherein the determining whether the four memory cells have the common physical structure in the layout according to the parity of the sum comprises one of: Calculating the sum of the row coordinates and the column coordinates of the failure storage unit with the physical coordinates of the upper right corner, wherein the contact holes are arranged under the condition that the sum is even; And calculating the sum of the row coordinates and the column coordinates of the failure memory cell with the physical coordinates of the left lower corner, wherein the contact hole exists when the sum is even, and the contact hole does not exist when the sum is odd.
6. The method of claim 1, wherein the failure type comprises a single bit failure type, a double bit failure type, a first four bit failure type, a line local failure type, and a cluster failure type, wherein the physical address comprises physical coordinates, wherein after the failed memory cell is classified according to a preset layout structure rule and the physical address, the method further comprises: determining a physical influence range according to the physical coordinates of the failure type for each failure type; determining the dependency relationship between failure types according to the inclusion relationship between the physical influence ranges; and sequencing all failure types based on the dependency relationship to generate a priority sequence.
7. A failure type determining apparatus of a storage unit, the apparatus comprising: the device comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring test data corresponding to a failure storage unit in a memory, and the test data comprises a logic address of the failure storage unit in the memory; The mapping module is used for mapping the logical address into a physical address of the failure storage unit in the memory layout; The classification module is used for classifying the failure storage units according to preset layout structure rules and the physical addresses and determining failure types, wherein the layout structure rules comprise association relations between common physical structures and physical addresses of a memory layout.
8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 6 when the computer program is executed.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.
10. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.

Description

Method and device for determining failure type of storage unit and computer equipment Technical Field The present application relates to the field of memory failure technology, and in particular, to a method, an apparatus, a computer device, a computer readable storage medium, and a computer program product for determining a failure type of a storage unit. Background Static Random Access Memory (SRAM) is widely used in caches, embedded systems and other scenarios where fast access to data is required. However, the continuous shrinking process size and increasing integration make the problem of SRAM failure increasingly prominent, and the types of SRAM failure are mainly classified into hard failure (Hard Failures) and soft failure (Soft Failures), wherein soft failure is mainly a transient failure, and is usually caused by external environmental factors (such as radiation and noise interference) or internal circuit characteristics (such as charge sharing and voltage fluctuation), and is represented by data inversion or read-write errors. While hard failures are typically caused by manufacturing defects, material aging, or physical damage, and are manifested as permanent loss of functionality, such as open circuits, shorts, or transistor threshold voltage shifts, etc., such failures need to be mitigated by techniques such as process improvement, redundant design, or Error Correction Code (ECC). In the chip manufacturing process, the SRAM failure type classification analysis failure cause is deeply known, and is optimized by combining with the actual application scene, so that the method has important significance for improving the yield and reliability of the SRAM, and the premise is that the failure unit is accurately found out from tens of millions of units for analysis. In practical applications, the failure types are generally simply divided according to the failure positions of the memory cell bits, for example, we divide four memory cell bits that fail simultaneously into four-bit failure types QB fail, but there is no deeper analysis of the influence of the common position on the failure type division, which may cause erroneous judgment of the failure types. Disclosure of Invention In view of the foregoing, it is desirable to provide a failure type determining method, apparatus, computer device, computer readable storage medium, and computer program product for a storage unit that can improve the accuracy of failure classification. In a first aspect, the present application provides a method for determining a failure type of a storage unit, the method comprising: Obtaining test data corresponding to a failure storage unit in a memory, wherein the test data comprises a logic address of the failure storage unit in the memory; Mapping the logical address into a physical address of the invalid storage unit in a memory layout; And classifying the failure storage units according to preset layout structure rules and the physical addresses to determine failure types, wherein the layout structure rules comprise association relations between common physical structures and physical addresses of a memory layout. In one embodiment, the mapping the logical address to the physical coordinates of the failed memory cell in the memory layout includes: converting the logical address into a physical block address, a memory block address, a segment address, a word line address, and a bit line address; Determining a storage area of the failure storage unit in a memory layout based on the physical block address, the storage block address and the segment address; the row coordinates of the failed memory cell within the memory region are determined based on the word line address, and the column coordinates of the failed memory cell within the memory region are determined based on the bit line address. In one embodiment, the failure types include a first four-bit failure type and a second four-bit failure type, wherein the second four-bit failure type includes two-bit failure modes or four single-bit failure modes, the step of classifying the failure storage unit according to a preset layout structure rule and the physical coordinates, and the step of determining the failure type includes: If the physical coordinates of the four failed storage units are detected to meet the matrix of 2 x 2, selecting one physical coordinate from the physical coordinates of the four failed storage units as a physical coordinate of a reference point; calculating the sum of row coordinates and column coordinates of the datum points, and judging whether the four storage units have a shared physical structure in the layout according to the parity of the sum; If the shared physical structure exists, judging that the four failure storage units belong to the first four-bit failure type; And if the shared physical structure does not exist, judging that the four failure storage units belong to the second four-bit failure type. In one embodiment, the ref