CN-122000155-A - Piezoresistor packaging structure and packaging method

Abstract

The invention discloses a piezoresistor packaging structure and a packaging method, comprising the following steps of stacking a bare chip A and a bare chip B in parallel, then mounting on a substrate and packaging, grinding the packaging top surface until the surface of the bare chip A is exposed, vertically etching packaging materials to form a groove, electroplating a first circuit in the groove, electroplating and extending to the surface of the bare chip A, continuing packaging the first circuit, overturning the packaging body up and down, re-mounting, exposing the bare chip B in a flush manner on the packaging body, penetrating and etching the bare chip B to the bare chip A, forming a through hole, electroplating a second circuit in the through hole and extending to the packaging surface, connecting the first circuit with the bare chip B through an electroplating circuit III, packaging the second circuit and the third circuit, grinding and exposing, electroplating pins on the exposed second circuit and the exposed third circuit, peeling off the substrate and cutting into a product unit of the packaging body.

Inventors

• WANG YAKE
• TAN XIAOCHUN

Assignees

• 合肥矽迈微电子科技有限公司

Dates

Publication Date

20260508

Application Date

20260209

Claims (10)

1. 1. The piezoresistor packaging method is characterized by comprising the following steps of: packaging, namely stacking the bare chip A and the bare chip B in parallel, mounting on a substrate, packaging, and grinding the top surface of the packaging until the surface of the bare chip A is exposed; Etching and electroplating, namely vertically etching the encapsulating material to form a groove, electroplating a first circuit in the groove, electroplating to extend to the surface of the bare chip A, and continuing to encapsulate the first circuit; Turning the encapsulation body upside down for re-mounting, exposing the bare chip B in a flush way on the encapsulation body, penetrating and etching the bare chip B to the bare chip A to form a via hole, electroplating a second circuit in the via hole and extending to the encapsulation surface, connecting the first circuit with the bare chip B through an electroplating circuit III, encapsulating the second circuit and the third circuit, and grinding and exposing; electroplating pins, namely electroplating pins on the exposed second circuit and the exposed third circuit, stripping the substrate and cutting the substrate into package product units.
2. 2. The method according to claim 1, wherein in the mounting and packaging step, the copper-clad double-sided die a and the copper-clad double-sided die B are stacked in parallel by using a thermally and electrically conductive adhesive, and the stacked structure is then mounted on the substrate after being cut and separated into a plurality of groups of stacked structures of the die a and the die B.
3. 3. The method of claim 2, wherein in the rotating plate etching step, the etched via avoids an active area of die B.
4. 4. The method of claim 3, wherein in the rotating plate etching step, the exposed copper-clad surface of the die B is etched to form a cross section during the etching of the via hole, and the electrical connection between the second circuit and the entire exposed copper-clad surface of the die B is cut off.
5. 5. The method of claim 1, wherein in the rotating plate etching step, a second circuit electroplated in the via electrically leads the die a and the die B in parallel to the leads, and out of the package through the leads.
6. 6. The utility model provides a piezo-resistor packaging structure, includes the encapsulation body, its characterized in that, encapsulation has in the encapsulation body: Die, die a and die B are stacked in parallel up and down; the first circuit is electrically connected with the bare chip A after etching the groove in the packaging body, and electrically leads the bare chip A out of the packaging body; A second circuit, which is used for forming a via hole by penetrating and etching the bare chip B to the bare chip A, electroplating the second circuit in the via hole, and electrically leading the bare chip A and the bare chip B out of the package body in parallel; And the third circuit is electrically connected with the first circuit, and the other electrical property of the parallel circuit of the die A and the die B is led out of the package body.
7. 7. The varistor package structure of claim 6, wherein the die a double-sided copper-clad core is stacked in parallel with die B double-sided copper-clad core by thermally and electrically conductive adhesive, and cut to separate into multiple sets of stacked structures of die a and die B.
8. 8. The package structure of claim 7, wherein the via is etched away from the active area of die B.
9. 9. The package structure of claim 8, wherein the exposed copper surface of die B is etched to form a cross-section during the etching of the via hole, thereby cutting off the electrical connection between the second circuit and the entire exposed copper surface of die B.
10. 10. The varistor package structure of claim 6, wherein the third and second traces are plated with pins, the pins being plated outside the package to electrically lead the second and third traces out of the package, respectively.

Description

Piezoresistor packaging structure and packaging method Technical Field The invention belongs to the technical field of chip packaging, and particularly relates to a piezoresistor packaging structure and a piezoresistor packaging method. Background The piezoresistor is a core universal device for overvoltage and surge protection, and is applied to cover almost all scenes needing overvoltage and surge protection, such as low-voltage micro-electricity, civil electronics, industrial equipment, power grids, new energy, automobile electronics and the like, by virtue of the characteristics of high response speed, adjustable through-flow capability, low cost and flexible volume, and the voltage, through-flow and space requirements of different scenes are precisely matched by different packaging types. The piezoresistor is packaged in parallel, the total current capacity is increased, surge current can be uniformly distributed to each chip core body, the single chip body is prevented from being broken down and burned, the conventional packaging parallel structure is that the piezoresistor is respectively packaged and then welded to a working area (such as a circuit board) in parallel, a large space is occupied, and the conventional packaging technology for stacking bare chips is difficult to meet the requirement of small-size packaging or the performance of products with the same packaging size is limited. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a piezoresistor packaging structure and a piezoresistor packaging method. In order to achieve the above object, the present invention provides a method for packaging a varistor, comprising the following steps: packaging, namely stacking the bare chip A and the bare chip B in parallel, mounting on a substrate, packaging, and grinding the top surface of the packaging until the surface of the bare chip A is exposed; Etching and electroplating, namely vertically etching the encapsulating material to form a groove, electroplating a first circuit in the groove, electroplating to extend to the surface of the bare chip A, and continuing to encapsulate the first circuit; Turning the encapsulation body upside down for re-mounting, exposing the bare chip B in a flush way on the encapsulation body, penetrating and etching the bare chip B to the bare chip A to form a via hole, electroplating a second circuit in the via hole and extending to the encapsulation surface, connecting the first circuit with the bare chip B through an electroplating circuit III, encapsulating the second circuit and the third circuit, and grinding and exposing; electroplating pins, namely electroplating pins on the exposed second circuit and the exposed third circuit, stripping the substrate and cutting the substrate into package product units. Further, in the mounting and packaging step, the copper-clad double-sided core of the bare chip A and the copper-clad double-sided core of the bare chip B are stacked in parallel through the heat-conducting adhesive, the surface is etched, then vertically cut and separated into a plurality of groups of stacked structures of the bare chip A and the bare chip B, and the stacked structures are mounted on the substrate. Further, in the rotating plate etching step, the etched via hole avoids the effective area of the die B. Further, in the rotating plate etching step, when the via hole is etched, the exposed copper-clad surface of the bare chip B is etched to form a cross section, and the electrical connection between the second circuit and the whole exposed copper-clad surface of the bare chip B is cut off. Further, in the rotating plate etching step, the second electroplated circuit in the through hole electrically leads the bare chip A and the bare chip B out of the package body in parallel to the pin, and leads the bare chip A and the bare chip B out of the package body through the pin. A piezoresistor packaging structure comprises a packaging body, wherein the packaging body is internally encapsulated with: Die, die a and die B are stacked in parallel up and down; the first circuit is electrically connected with the bare chip A after etching the groove in the packaging body, and electrically leads the bare chip A out of the packaging body; A second circuit, which is used for forming a via hole by penetrating and etching the bare chip B to the bare chip A, electroplating the second circuit in the via hole, and electrically leading the bare chip A and the bare chip B out of the package body in parallel; And the third circuit is electrically connected with the first circuit, and the other electrical property of the parallel circuit of the die A and the die B is led out of the package body. Further, the double-sided copper-clad core of the bare chip A and the double-sided copper-clad core of the bare chip B are stacked in parallel through the heat-conducting and electric-conducting adhesive, and are cut and separated into