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CN-122000201-A - Multilayer electronic component

CN122000201ACN 122000201 ACN122000201 ACN 122000201ACN-122000201-A

Abstract

A multilayer electronic component is disclosed that includes a body having first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other, and fifth and sixth surfaces opposing each other. The body includes a stack region having dielectric layers and internal electrodes alternately arranged in a first direction, a first edge region between the stack region and the third surface, and a second edge region between the stack region and the fourth surface. The first and second external electrodes are disposed on the third and fourth surfaces, respectively. The first and second via electrodes pass through the first and second edge regions, respectively. And/or 3≤R1≤7% and/or 3≤R2≤7%, wherein, in a cross section of the body in the second direction and the third direction, R1 represents a ratio of an area of the first via electrode to an area of the first edge region, and R2 represents a ratio of an area of the second via electrode to an area of the second edge region.

Inventors

  • LI ZHIXUN
  • JIN XIANGYE
  • JIN TAIRONG

Assignees

  • 三星电机株式会社

Dates

Publication Date
20260508
Application Date
20250814
Priority Date
20241106

Claims (12)

  1. 1. A multilayer electronic assembly comprising: A body having first and second surfaces opposite to each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposite to each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposite to each other in a third direction, the body including a stacked region including a dielectric layer and first and second internal electrodes alternately arranged in the first direction with the dielectric layer interposed therebetween, a first edge region disposed between the stacked region and the third surface, in which there is no second internal electrode, and a second edge region disposed between the stacked region and the fourth surface, in which there is no first internal electrode; first and second external electrodes disposed on the third and fourth surfaces, respectively, and connected to the first and second internal electrodes, respectively, and First and second via electrodes passing through the first and second edge regions, respectively, and connected to the first and second internal electrodes, respectively; At least one of 3% or less than or equal to R1 or less than 7% and 3% or less than or equal to R2 or less than 7% is satisfied, wherein, in a cross section of the main body in the second direction and the third direction, R1 is a ratio of an area of the first via electrode to an area of the first edge region, and R2 is a ratio of an area of the second via electrode to an area of the second edge region.
  2. 2. The multilayer electronic component of claim 1, Wherein the first through hole electrode and the second through hole electrode are arranged in a plurality, Wherein the area of the first via electrode is a total area of a plurality of the first via electrodes, Wherein the area of the second via electrode is a total area of a plurality of the second via electrodes.
  3. 3. The multilayer electronic component of claim 2, Wherein a plurality of the first via electrodes are arranged along the third direction, Wherein a plurality of the second via electrodes are arranged along the third direction.
  4. 4. The multilayer electronic component of claim 1, Wherein a ratio of L1a to L1 is 5% or more, wherein L1 is a length of the first edge region in the second direction, and L1a is a distance between the third surface and the first via electrode in the second direction.
  5. 5. The multilayer electronic component of claim 1, Wherein a ratio of L1b to L1 is 5% or more, wherein L1 is a length of the first edge region in the second direction, and L1b is a distance between the overlap region and the first via electrode in the second direction.
  6. 6. The multilayer electronic component of claim 1, Wherein D1 is 5 μm or more, wherein D1 is a diameter of the first via electrode.
  7. 7. The multilayer electronic component according to claim 3, Wherein a ratio of D2 to D1 is 1.2 or more, wherein D1 is a diameter of the first via electrode, and D2 is a distance between adjacent two of the plurality of first via electrodes.
  8. 8. The multilayer electronic component of claim 7, Wherein the ratio of D2 to D1 is less than or equal to 2.5.
  9. 9. The multilayer electronic component of claim 1, Wherein the first external electrode is disposed to extend from the third surface to the first surface and the second surface, Wherein the second external electrode is arranged to extend from the fourth surface onto the first surface and the second surface, Wherein the first via electrode is exposed to the first surface and the second surface and is connected to the first external electrode, Wherein the second via electrode is exposed to the first surface and the second surface and is connected to the second external electrode.
  10. 10. The multilayer electronic component of claim 1, Wherein the first internal electrode includes a first main portion provided in the overlap region and overlapping the second internal electrode, and a first lead-out portion provided in the first edge region and extending from the first main portion and exposed to the third surface, Wherein the second internal electrode includes a second main portion disposed in the overlap region and overlapping the first internal electrode, and a second lead-out portion disposed in the second edge region and extending from the second main portion and exposed to the fourth surface.
  11. 11. The multilayer electronic component of claim 1, Wherein, in the cross section of the main body in the second direction and the third direction, the cross section of the first via electrode and the cross section of the second via electrode are circular.
  12. 12. The multilayer electronic component of claim 10, Wherein the first via electrode is connected to a plurality of first lead-out portions of a plurality of the first internal electrodes and spaced apart from a plurality of the second internal electrodes, and Wherein the second via electrode is connected to a plurality of second lead-out portions of the plurality of second internal electrodes and is spaced apart from the plurality of first internal electrodes.

Description

Multilayer electronic component The present application claims the benefit of priority from korean patent application No. 10-2024-0156140 filed in the korean intellectual property office on day 11 and 6 of 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates to a multilayer electronic assembly. Background A multilayer ceramic capacitor (MLCC, a type of multilayer electronic component) is a chip capacitor mounted on and used to charge or discharge various types of electronic products such as printed circuit boards of image display devices including Liquid Crystal Displays (LCDs) and Plasma Display Panels (PDPs), computers, smart phones, and mobile phones. Such a multilayer ceramic capacitor can be used as a component in various electronic devices due to its small size, ensuring high capacitance, and ease of installation. Recently, as the performance of electronic products mounted with MLCCs increases, MLCCs achieving higher and uniform capacitance are required. However, capacitance distribution and ESR distribution may occur due to poor contact between the inner electrode and the outer electrode of the MLCC. In order to solve these problems, there is a method of manufacturing a hole in a main body and providing a via electrode connecting internal electrodes of the same polarity. (Patent document 1) Japanese patent No. 2004-281957. Disclosure of Invention An aspect of the present disclosure is to provide a multilayer electronic component having excellent electrical characteristics. However, the problems to be solved by the present disclosure are not limited to the above, and will be more easily understood in describing specific embodiments of the present disclosure. A body having first and second surfaces opposite to each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposite to each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposite to each other in a third direction, the body including a stack region including a dielectric layer and first and second internal electrodes alternately arranged in the first direction with the dielectric layer interposed therebetween, a first edge region disposed between the stack region and the third surface, the second edge region disposed between the stack region and the fourth surface, the second edge region not being present therein; and first and second via electrodes passing through the first and second edge regions and connected to the first and second inner electrodes, respectively, wherein the multilayer electronic component satisfies at least one of 3% or less R1 7% or less and 3% or less R2% or less, wherein R1 is a ratio of an area of the first via electrode to an area of the first edge region in a cross section of the body in the second and third directions, and R2 is a ratio of an area of the second via electrode to an area of the second edge region. Drawings The foregoing and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: fig. 1 is a perspective view schematically illustrating a multilayer electronic assembly according to an embodiment of the present disclosure. Fig. 2 schematically shows a cross-sectional view taken along the line I-I' of fig. 1. Fig. 3 schematically shows a cross-section taken along the line II-II' of fig. 1. Fig. 4 schematically shows a cross-sectional view taken along line III-III' of fig. 2. Fig. 5 is a cross-sectional view of fig. 4 with the inner electrode and the via electrode removed, schematically illustrating the area of the edge region. Fig. 6 is a cross-sectional view of fig. 4 with the inner electrode removed, schematically illustrating the area of the via electrode. Detailed Description Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the embodiments of the present disclosure may be modified into various other forms, and the scope of the present disclosure is not limited to the embodiments described below. Further, embodiments of the present disclosure may be provided to more fully describe the present disclosure to one of ordinary skill in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clarity of description, and elements denoted by the same reference numerals in the drawings may be the same elements. In the drawings, portions irrelevant to the description will be omitted for the purpose of clarifying the present disclosure, and thicknesses may be exaggerated to clearly show layers and regions. The same reference numerals will be used to denote components having the same functions within the same concept. Furthermore, throughout the specification, when an element is referred to as