Search

CN-122000849-A - Circuit for improving ESD (electro-static discharge) capability of RS485 interface chip

CN122000849ACN 122000849 ACN122000849 ACN 122000849ACN-122000849-A

Abstract

The invention discloses a circuit for improving the ESD capacity of an RS485 interface chip, which is characterized in that a branch for detecting ESD current is added between a bus port and the ground, a node signal Vs on a sampling resistor Rs is monitored in real time, and when the bus port is subjected to ESD electrostatic discharge, a power output NMOS tube in the chip can be rapidly turned off through a logic control circuit, so that the RS485 bus port instantly enters a high-resistance state, a low-resistance discharge passage of an ESD positive charge to the ground in the prior art is disconnected, the hidden danger that an ESD protection device (SCR) is difficult to trigger or trigger hysteresis is eliminated, the reliable discharge of the ESD charge from the SCR is ensured, the negative influence of process deviation, voltage and temperature change on the electrostatic protection performance of the chip is effectively overcome, and the ESD tolerance, robustness and mass production consistency of the bus port of the interface chip are remarkably improved.

Inventors

  • XIE PENG
  • WU YIKANG

Assignees

  • 深圳市华普微电子股份有限公司
  • 无锡泽太微电子有限公司

Dates

Publication Date
20260508
Application Date
20260409

Claims (10)

  1. 1. The circuit for improving the ESD capacity of the RS485 interface chip comprises an RS485 bus port, a power output stage and an ESD protection device connected in parallel between the RS485 bus port and the ground, and is characterized by further comprising an ESD event detection circuit; The power output stage comprises a power diode drop, a PMOS tube, a first NMOS tube NM1 and a second NMOS tube NM2, wherein the first NMOS tube NM1 is used as a main passage of the power output stage, the second NMOS tube NM2 is connected with a sampling resistor Rs in series and then is used as a secondary passage of the power output stage to be connected to the ground GND, and the connection point of the second NMOS tube NM2 and the sampling resistor Rs is defined as a node signal Vs; the input end of the ESD event detection circuit is connected with the node signal Vs, and the output end of the ESD event detection circuit is respectively connected with the grid electrodes of the first NMOS tube NM1 and the second NMOS tube NM 2; When an ESD event is detected, the ESD event detection circuit outputs a control signal to disconnect the first NMOS transistor NM1 and the second NMOS transistor NM2, so that the RS485 bus port enters a high-resistance state, and ESD charge is forced to bleed through the ESD protection device.
  2. 2. The circuit for improving ESD capability of an RS485 interface chip of claim 1, wherein the first NMOS transistor NM1 and the second NMOS transistor NM2 are sized in a ratio such that the first NMOS transistor NM1 outputs 95% of current and the second NMOS transistor NM2 outputs 5% of current.
  3. 3. The circuit for improving ESD ability of an RS485 interface chip according to claim 1, wherein the ESD event detection circuit comprises a first inverter Inv1, an RS latch, a D flip-flop, a second inverter Inv2, a third inverter Inv3, a fourth inverter Inv4, a Nand gate Nand2, a Nor gate Nor, and a delay unit; The node signal Vs is connected to an input of the first inverter Inv1, and an output of the first inverter Inv1 is defined as a node signal Vrs1; the node signal Vrs1 is connected to the first input of the RS latch while being connected to the input of the second inverter Inv 2; The output end of the second inverter Inv2 is connected to the clock input end Clk of the D trigger, and the data input end D of the D trigger is connected to the power supply voltage VDD; The output terminal Q of the D trigger is connected to the second input terminal of the RS latch and is defined as a node signal Vrs2; The output of the RS latch is connected to the input of the third inverter Inv3, the output of the third inverter Inv3 being defined as a node signal Vrso; The node signal Vrso is connected to the first input terminal of the Nand gate Nand2, the second input terminal of the Nand gate Nand2 is connected to the enable control signal EN, the output terminal of the Nand gate Nand2 is defined as a node signal Dctl, the node signal Dctl is connected to the first input terminal of the Nor gate Nor, the second input terminal of the Nor gate Nor is connected to the input signal Din, and the output terminal of the Nor gate Nor is defined as a node signal drvn; the node signal drvn is connected to the gates of the first NMOS transistor NM1 and the second NMOS transistor NM 2.
  4. 4. A circuit for improving ESD ability of an RS485 interface chip according to claim 3, wherein the node signal Dctl is further connected to the input of the fourth inverter Inv4, the output of the fourth inverter Inv4 is connected to the input of the delay unit, the output of the delay unit is defined as node signal Drst, and the node signal Drst is connected to the Reset input Reset of the D flip-flop; the Reset input Reset of the D flip-flop is active low.
  5. 5. A circuit for improving ESD ability of an RS485 interface chip according to claim 3, wherein the resistance of the sampling resistor RS is 70Ω; The logic threshold voltage of the first inverter Inv1 is set to 2.1V, corresponding to a 5V supply voltage condition; The trigger current threshold for an ESD event is set to 600mA.
  6. 6. The circuit for improving the ESD capability of the RS485 interface chip according to claim 1, wherein the ESD protection device is a bidirectional thyristor SCR structure; the trigger voltage of the bidirectional thyristor SCR structure is higher than the normal working voltage of the RS485 bus port and lower than the highest withstand voltage value of the output circuit in the chip.
  7. 7. A circuit for improving ESD ability of an RS485 interface chip according to claim 3, wherein the delay unit is configured to delay the output signal of the fourth inverter Inv4 by 1us and output it to the node signal Drst after detecting the triggering of the ESD event, so as to maintain the off state of the first NMOS transistor NM1 and the second NMOS transistor NM2 for 1us time.
  8. 8. The circuit for improving ESD ability of RS485 interface chip according to claim 3, wherein in normal operation mode, when enable control signal en=1 and input signal din=0, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, and the RS485 bus port outputs low level; at this time, if the RS485 bus port flows through the maximum working current 60mA, the sampling current of the second NMOS transistor NM2 branch is 3mA, the voltage drop generated on the sampling resistor RS is 210mV, this voltage is far lower than the logic inversion threshold voltage of the first inverter Inv1, and the output of the node signal Vrs1 is kept at a high level, so as to ensure that the normal working current cannot be triggered as an ESD event by mistake.
  9. 9. The circuit of claim 3, wherein when an ESD event occurs and the transient current exceeds 600mA, the transient current of the second NMOS transistor NM2 branch flows through the sampling resistor RS, a voltage greater than 2.1V is generated on the node signal Vs, so that the node signal Vrs1 is turned to a low level, the RS latch is turned to a high level, the node signal Vrso is outputted, the node signal Dctl is turned to a high level, the node signal drvn is turned to a low level, the first NMOS transistor NM1 and the second NMOS transistor NM2 are disconnected, the node signal Vs is pulled down to a low level by the resistor RS, the node signal Vrs1 is outputted to a high level through the first inverter Inv1, the node signal Drst maintains a high level for 1us time due to the effect of the delay unit, the node signal Vrs2 is also turned to a high level, the input signal of the RS latch is turned to a high level, and the output state 1us remains unchanged for a time period, thereby keeping the first NMOS transistor NM1 and the second NMOS transistor NM2 disconnected.
  10. 10. A circuit for improving ESD capability of an RS485 interface chip according to claim 3, wherein when an ESD event is completed and a delay time set by the delay unit has elapsed, the node signal Drst goes low to reset the D flip-flop, the node signal Vrs2 goes low, the node signal Vrso returns to high, the node signal Dctl returns to low, the outputs of the node signals drvn and drvp are controlled again by the input signal Din, and the RS485 bus port returns to a normal operation state.

Description

Circuit for improving ESD (electro-static discharge) capability of RS485 interface chip Technical Field The invention relates to the technical field of integrated circuits, in particular to a circuit for improving the ESD capacity of an RS485 interface chip. Background The RS485 interface chip is widely applied to the communication fields of automobile electronics, internet of things, aerospace and the like, is mainly used as an interface for signal acquisition, transmission and remote communication, and needs to support hot plug and meet the requirements of high-reliability communication. In order to ensure the working stability of the chip under severe environment, the protection of electrostatic discharge (ESD) is extremely high. Test standards were established by the International Electrotechnical Commission (IEC) for evaluating the ESD protection capability of electronic systems, with IEC61000-4-2 contact discharge and air discharge being the two most common methods used in ESD testing. For the RS485 interface chip, the ESD protection capability of the bus port is required to reach contact discharge + -15 kV. Currently, to achieve such high levels of ESD protection, only the most current sinking thyristor (SCR) structures are used. A common ESD protection scheme for an RS485 interface chip is shown in fig. 1. The working voltage range of the RS485 bus port is-7V to +12V, so that the power output stage needs to adopt a stacked structure of a diode and an MOS tube, and the ESD protection device adopts a bidirectional silicon controlled SCR structure (shown in figure 1). The ESD protection device is connected in parallel with the bus port, and the trigger voltage of the ESD protection device is required to be higher than the normal working voltage of the bus port and lower than the highest withstand voltage value of the output circuit inside the chip. When the bus port generates ESD event, the instant high voltage can make the reverse biased junction of NPN2 generate avalanche breakdown, the generated carrier flows through parasitic resistance Rpar2 to make parasitic triode NPN2 conduct and trigger NPN2 and PNP to form positive feedback, the SCR device enters into the negative resistance region to form a low resistance passage capable of effectively discharging ESD charge, thereby realizing the protection of the internal circuit of the chip. The worst case ESD protection capability of the bus port, as analyzed by the circuit, occurs when the port output is low. When the control signals en=1 and din=0, the diode Dion and the NMOS in fig. 1 are both in a conductive state, a low-impedance discharging path is formed between the bus port and the ground, and the positive ESD charge can discharge the charge through the path, which may cause the ESD protection device SCR to be not triggered in time or even not triggered, thereby causing damage to the internal circuit of the chip. The trigger voltage of the SCR device is closely related to the device size, PN junction distance, doping concentration and the like, and technological deviation exists in the parameters in the semiconductor technology, so that the trigger voltage of the SCR device is changed, and meanwhile, the worst ESD protection capability is considered, and the on-resistance of the diode Dion and the NMOS is changed along with the technological deviation, the power supply voltage and the temperature. The dual variation factor may significantly reduce the robustness of the chip. Laboratory sampling tests show that when one batch of RS485 chips are configured to output high resistance through a bus port, the ESD protection capacity reaches more than +/-15 kV of contact discharge, and when the other batch of RS485 chips are configured to output low level through the bus port, the middle value of the ESD protection capacity is +/-15 kV of contact discharge, the maximum value can reach +/-20 kV, and the minimum value is only +/-10 kV. Because the ESD protection capability of the RS485 interface chip is determined by the minimum value under each test condition, the robustness problem can lead to the reduction of the ESD protection parameters of the chip, and an ESD protection device with higher requirements needs to be designed, so that the design difficulty of the chip and the development period of products are increased. Disclosure of Invention The invention aims to provide a circuit for improving the ESD capacity of an RS485 interface chip, which ensures that an SCR (selective catalytic reduction) of an ESD protection device can be triggered in time and protects an internal circuit of the chip. The robustness of the chip can be greatly improved, and the ESD protection parameters of the chip can be improved. In order to achieve the purpose, the technical scheme adopted by the invention is that the circuit for improving the ESD capacity of the RS485 interface chip comprises an RS485 bus port, a power output stage, an ESD protection device connected in pa