CN-122001066-A - Integrated circuit with power-down protection function

Abstract

The application discloses an integrated circuit with a power-down protection function, which comprises a bus terminal, an energy storage terminal, a charging circuit and a capacitance detection circuit, wherein the bus terminal is used for providing a bus voltage, the energy storage terminal is coupled to the power-down protection capacitor, the charging circuit is coupled between the bus terminal and the energy storage terminal and is configured to charge the power-down protection capacitor by using the bus voltage, the charging circuit comprises a first charging path and is configured to provide a first constant charging current to the power-down protection capacitor to charge the power-down protection capacitor based on the bus voltage in the starting process of the integrated circuit so as to enable the voltage at two ends of the power-down protection capacitor to rise with a first fixed slope, and the capacitance detection circuit is configured to monitor the voltage at two ends of the power-down protection capacitor in the period of charging the power-down protection capacitor through the first charging path in the starting process of the integrated circuit so as to acquire parameters for calculating the capacitance value of the power-down protection capacitor.

Inventors

• YANG HANG
• LI BO
• WANG HAITANG
• LAI PENGJIE

Assignees

• 成都芯源系统有限公司

Dates

Publication Date

20260508

Application Date

20241105

Claims (20)

1. 1. An integrated circuit with power down protection function, comprising: A bus terminal configured to provide a bus voltage; an energy storage terminal configured to be coupled to a power-down protection capacitor; A charging circuit coupled between the bus terminal and the energy storage terminal and configured to charge the power down protection capacitor with the bus voltage, wherein the charging circuit includes a first charging path configured to provide a first constant charging current based on the bus voltage to charge the power down protection capacitor during start-up of the integrated circuit such that a voltage across the power down protection capacitor rises with a first fixed slope, and And the capacitance detection circuit is configured to monitor the voltage at two ends of the power-down protection capacitor during the period of charging the power-down protection capacitor through the first charging path in the starting process of the integrated circuit so as to acquire parameters for calculating the capacitance value of the power-down protection capacitor.
2. 2. The integrated circuit of claim 1, wherein the capacitance detection circuit is configured to obtain a first time during which a voltage across the power down protection capacitor rises from a first threshold voltage to a second threshold voltage during a start-up of the integrated circuit during a first charging path providing the first constant charging current to charge the power down protection capacitor, wherein the second threshold voltage is higher than the first threshold voltage, wherein the parameter comprises the first time.
3. 3. The integrated circuit of claim 2, wherein the capacitance detection circuit is further configured to obtain a capacitance value of the power down protection capacitor based at least on the first time, the first threshold voltage, the second threshold voltage, and the first constant charging current.
4. 4. The power management current of claim 2, wherein the capacitance detection circuit is configured to obtain the capacitance value of the power down protection capacitor based at least on the following equation: C=I CH1 *T1/(V TH2 -V TH1 ), Wherein, C represents a capacitance value of the power-down protection capacitor, I CH1 represents the first constant charging current value, V TH1 represents the first threshold voltage, V TH2 represents the second threshold voltage, and T1 represents the first time.
5. 5. The integrated circuit of claim 1, wherein the first charging path is further configured to provide a second constant charging current to charge the power down protection capacitor during start-up of the integrated circuit, Wherein the period during which the first charging path charges the power-down protection capacitor includes a first constant charging period and a second constant charging period, Wherein the first charging path is configured to provide the first constant charging current to the power down protection capacitor to charge the power down protection capacitor during the first constant charging period, to cause a voltage across the power down protection capacitor to rise at the first fixed slope, and to provide the second constant charging current to the power down protection capacitor to charge the power down protection capacitor during the second constant charging period, to cause a voltage across the power down protection capacitor to rise at the second fixed slope, Wherein the first constant charging current is not equal to and proportional to the second constant charging current.
6. 6. The integrated circuit of claim 5, wherein the capacitance detection circuit is configured to obtain a first time during which the voltage across the power down protection capacitor rises from the first threshold voltage to the second threshold voltage, and to obtain a second time during which the voltage across the power down protection capacitor rises from a third threshold voltage to a fourth threshold voltage during the second constant charge, wherein the parameters include the first time and the second time, wherein the fourth threshold voltage is higher than the third threshold voltage and the second threshold voltage is higher than the first threshold voltage.
7. 7. The integrated circuit of claim 6, wherein the third threshold voltage is equal to the first threshold voltage and the fourth threshold voltage is equal to the third threshold voltage.
8. 8. The integrated circuit of claim 6, wherein the difference between the second threshold voltage and the first threshold voltage and the difference between the fourth threshold voltage and the third threshold voltage are proportional.
9. 9. The integrated circuit of claim 6, wherein a difference between the second threshold voltage and the first threshold voltage is equal to a difference between the fourth threshold voltage and the third threshold voltage.
10. 10. The integrated circuit of claim 9, wherein the capacitance detection circuit is configured to obtain the capacitance value of the power-down protection capacitor based at least on the first time, the second time, the first threshold voltage, the second threshold voltage, the first constant charging current, a ratio of the first constant charging current to the second constant charging current.
11. 11. The integrated circuit of claim 9, wherein the capacitance detection circuit is configured to obtain the capacitance value of the power down protection capacitor based on the following equation: C=(K1-1)*T1*T2*I CH1 /(T1-T2)*(V TH2 -V TH1 ), wherein, C represents a capacitance value of the power-down protection capacitor, I CH1 represents the first constant charging current value, K1 represents a ratio of the second constant charging current to the first constant charging current, T1 represents the first time, T2 represents the second time, V TH1 represents the first threshold voltage, and V TH2 represents the second threshold voltage.
12. 12. A method of detecting capacitance of a power-down protection capacitor, the method performed by an integrated circuit having a power-down protection function, and comprising: During start-up of the integrated circuit, providing a first constant charging current to the power down protection capacitor based on a bus voltage to charge the power down protection capacitor, causing a voltage across the power down protection capacitor to rise at a first fixed slope, and During the starting process of the integrated circuit, the voltage at two ends of the power-down protection capacitor is monitored during the period of charging the power-down protection capacitor by using a first constant charging current so as to obtain a parameter for calculating the capacitance value of the power-down protection capacitor.
13. 13. The method of claim 12, wherein the obtaining parameters for calculating the capacitance value of the power down protection capacitor comprises: And during the starting process of the integrated circuit, during the period of charging the power-down protection capacitor through the first constant charging current, acquiring a first time when the voltage at two ends of the power-down protection capacitor rises from a first threshold voltage to a second threshold voltage, wherein the second threshold voltage is higher than the first threshold voltage, and the parameter comprises the first time.
14. 14. The method of claim 13, further comprising: a capacitance value of the power down protection capacitor is obtained based at least on the first time, the first threshold voltage, the second threshold voltage, and the first constant charging current.
15. 15. The method of claim 13, further comprising: The capacitance value of the power-down protection capacitor is obtained based at least on the following equation: C=I CH1 *T1/(V TH2 -V TH1 ), Wherein, C represents a capacitance value of the power-down protection capacitor, I CH1 represents the first constant charging current value, V TH1 represents the first threshold voltage, V TH2 represents the second threshold voltage, and T1 represents the first time.
16. 16. The method of claim 12, further comprising: Providing the second constant charging current to the power down protection capacitor during start-up of the integrated circuit to charge the power down protection capacitor, Wherein the period during which the first charging path charges the power-down protection capacitor includes a first constant charging period and a second constant charging period, Wherein the first charging path is configured to provide the first constant charging current to the power down protection capacitor to charge the power down protection capacitor during the first constant charging period, to cause a voltage across the power down protection capacitor to rise at the first fixed slope, and to provide the second constant charging current to the power down protection capacitor to charge the power down protection capacitor during the second constant charging period, to cause a voltage across the power down protection capacitor to rise at the second fixed slope, Wherein the first constant charging current is not equal to and proportional to the second constant charging current.
17. 17. The method of claim 16, further comprising: During the first constant charge, a first time is obtained when the voltage across the power down protection capacitor rises from the first threshold voltage to the second threshold voltage, and during the second constant charge, a second time is obtained when the voltage across the power down protection capacitor rises from a third threshold voltage to a fourth threshold voltage, wherein the parameters include the first time and the second time, wherein the fourth threshold voltage is higher than the third threshold voltage, and the second threshold voltage is higher than the first threshold voltage.
18. 18. The method of claim 17, wherein the third threshold voltage is equal to the first threshold voltage and the fourth threshold voltage is equal to the third threshold voltage.
19. 19. The method of claim 17, wherein the difference between the second threshold voltage and the first threshold voltage and the difference between the fourth threshold voltage and the third threshold voltage are proportional.
20. 20. The method of claim 17, wherein a difference between the second threshold voltage and the first threshold voltage is equal to a difference between the fourth threshold voltage and the third threshold voltage.

Description

Integrated circuit with power-down protection function Technical Field The present application relates generally to electronic circuits, and more particularly, but not exclusively, to integrated circuits with power-down protection and methods of monitoring the capacitance of power-down protection capacitors. Background In some existing power management circuits, for uninterrupted power supply applications, a standby power supply is usually provided in order to enable the application device to continue to supply power when the external input voltage fails unexpectedly. For example, in conventional switching power supplies that provide bus voltage to downstream devices, such as in DC-DC voltage converters used to power Solid state drives (Solid STATE DRIVER, SSD), high-voltage capacitors with higher voltage ratings are often used as power-down protection capacitors to store energy when power is provided to the switching power supply and to release the stored energy as a backup power when preset conditions are met (e.g., when the bus voltage drops to a release threshold). It is known from the energy storage principle of a capacitor that the energy stored in the capacitor is proportional to the capacitance value of the capacitor. However, the capacitor ages over time and the capacitance decreases, which in turn reduces the energy it can store. In some applications, the power-down protection capacitor can not be used as a standby power supply when the stored energy is reduced to a certain extent. Therefore, it is necessary to effectively monitor the capacitance value of the power-down protection capacitor and reduce the influence of the monitoring action on the normal function. Disclosure of Invention An embodiment of the invention provides an integrated circuit with a power failure protection function, which comprises a bus terminal, an energy storage terminal, a charging circuit and a capacitance detection circuit. The bus terminal is configured to provide a bus voltage. The energy storage terminal is configured to be coupled to a power loss protection capacitor. The charging circuit is coupled between the bus terminal and the energy storage terminal and is configured to charge the power down protection capacitor with the bus voltage. The capacitance detection circuit is configured to monitor a voltage across the power down protection capacitor during a period in which the power down protection capacitor is charged through a first charging path during a start-up of the integrated circuit to obtain a parameter for calculating a capacitance value of the power down protection capacitor. The charging circuit includes a first charging path, and the first charging path is configured to provide a first constant charging current based on the bus voltage to charge the power down protection capacitor during start-up of the integrated circuit, causing a voltage across the power down protection capacitor to rise at a first fixed slope. The invention further provides a capacitance detection method of the power-down protection capacitor. The method is performed by an integrated circuit having a power-down protection function and comprises the following steps. During the start-up of the integrated circuit, a first constant charging current is provided to the power down protection capacitor based on a bus voltage to charge the power down protection capacitor, such that a voltage across the power down protection capacitor rises with a first fixed slope. During a start-up of the integrated circuit, a voltage across the power down protection capacitor is monitored during charging of the power down protection capacitor with a first constant charging current to obtain a parameter for calculating a capacitance value of the power down protection capacitor. It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows. Drawings For a better understanding of the present invention, embodiments thereof will be described with reference to the following drawings, which are for illustration only. The drawings generally depict only some of the features of the embodiments and are not necessarily drawn to scale. Fig. 1 shows a block diagram of a power management circuit with power-down protection according to an embodiment of the invention. Fig. 2 is a schematic circuit diagram showing a circuit configuration of the power management circuit shown in fig. 1 according to an embodiment of the present invention. Fig. 3 shows a waveform diagram of the stored voltage during charging of the power down protection capacitor according to an embodiment of the invention. Fig. 4 shows a waveform diagram of the stored voltage during constant current charging of the power down protection capacitor using the first charging path a