CN-122001180-A - Charge pump

CN122001180ACN 122001180 ACN122001180 ACN 122001180ACN-122001180-A

Abstract

The invention discloses a charge pump, relates to the technical field of charge pump driving, and aims to solve the problem that a charge pump in the prior art cannot generate working voltage required by a high-side power tube under low working voltage. The charge pump comprises a level processing module and a multi-stage charge pump module which are respectively connected with an oscillator, wherein the level processing module is used for generating a target voltage, inputting the target voltage into the oscillator, the target voltage is larger than or equal to a ground level and smaller than a power supply voltage, the oscillator is used for taking the target voltage as a ground level, taking an intermediate voltage as a high level to generate a target clock signal, inputting the target clock signal into the multi-stage charge pump module, the intermediate voltage is a secondary voltage generated after the power supply voltage is subjected to on-chip or off-chip voltage stabilization, the multi-stage charge pump is used for amplifying the intermediate voltage in multiple stages based on the target clock signal and outputting the intermediate voltage to a high-side power tube, and the charge pump can still normally output the voltage required by the high-side power tube under the lower working voltage.

Inventors

WANG TIAN
GUO GUILIANG

Assignees

北京中科银河芯科技有限公司

Dates

Publication Date: 20260508
Application Date: 20251222

Claims (10)

1. A charge pump, comprising: the system comprises a level processing module, an oscillator and a multi-stage charge pump module; The level processing module is connected with the oscillator, and the oscillator is connected with the multi-stage charge pump module; The level processing module is used for generating a target voltage, and inputting the target voltage into the oscillator, wherein the target voltage is larger than or equal to the ground level and smaller than the power supply voltage; the oscillator is used for taking the target voltage as a ground level, taking an intermediate voltage as a high level to generate a target clock signal, and inputting the target clock signal to the multi-stage charge pump module, wherein the intermediate voltage is a secondary voltage generated after the power supply voltage is subjected to on-chip or off-chip voltage stabilization; the multi-stage charge pump is used for amplifying the intermediate voltage in multiple stages based on the target clock signal and outputting the intermediate voltage to the high-side power tube.
2. The charge pump of claim 1, wherein the level processing module comprises a current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a first zener diode, and a second zener diode, wherein the fourth PMOS tube, the first NMOS tube, and the second NMOS tube are high voltage power MOS tubes; The source electrode of the first PMOS tube is connected with the power supply end, the grid electrode of the second PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the power supply end, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube is respectively connected with the drain electrode and the grid electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the second NMOS tube is respectively connected with the drain electrode and the grid electrode of the third PMOS tube, and the source electrode of the second NMOS tube is grounded; The grid electrode of the third PMOS is connected with a first terminal, the drain electrode of the fourth PMOS is grounded, the source electrode of the fourth PMOS is connected with the output end of the level processing module, the grid electrode of the fourth PMOS is connected with the first terminal, one end of the first resistor is connected with an intermediate voltage source end, the other end of the first resistor is connected with one end of the second resistor, the other end of the second resistor is respectively connected with the source electrode of the third PMOS and one end of the third resistor, the other end of the third resistor is connected with the first terminal, the negative electrode of the first Zener diode is connected with the intermediate voltage source end, the positive electrode of the first Zener diode is connected with the output end of the level processing module, the negative electrode of the second Zener diode is connected with the intermediate voltage source end, the positive electrode of the second Zener diode is connected with the first terminal, one end of the first capacitor is connected with the intermediate voltage source end, the other end of the first capacitor is connected with the output end of the level processing module, one end of the fourth resistor is connected with the intermediate voltage source end, the other end of the fourth resistor is connected with the output end of the level processing module, and the output end of the level processing module is connected with the ground plane end of the level processing module.
3. The charge pump of claim 2, wherein the third resistor and the fourth resistor in the level processing module are pull-up resistors for protecting the gate voltage and the target voltage of the third PMOS transistor; The first zener diode is used for limiting the lower limit of the target voltage, and the formula is adopted: ; representing a lower limit of the target voltage, wherein, Representing the target voltage, Represents an intermediate voltage, Representing the breakdown voltage of the zener diode; the second zener diode is used for limiting the upper limit of the target voltage, and the formula is adopted: ; representing an upper limit of the target voltage, wherein, Representing the threshold voltage of the fourth PMOS transistor.
4. The charge pump of claim 1, wherein the multi-stage charge pump module comprises at least a first stage charge pump module and a second stage charge pump module; the first-stage charge pump module is respectively connected with the oscillator and the second-stage charge pump module, and the second-stage charge pump module is connected with a high-side power tube; The first stage charge pump module is used for carrying out first stage amplification on the power supply voltage based on the target clock signal to obtain a first target voltage; the second stage charge pump module is used for performing second stage amplification on the first target voltage based on the target clock signal to obtain a second target voltage, and inputting the second target voltage to the high-side power tube.
5. The charge pump of claim 4, wherein the oscillator comprises a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal, wherein the first stage charge pump module comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor; One end of the second capacitor is connected with the first clock signal end, and the other end of the second capacitor is connected with a second terminal; the source electrode of the third NMOS tube is connected with the middle voltage source end, the drain electrode of the third NMOS tube is connected with the second terminal, and the grid electrode of the third NMOS tube is connected with the third terminal; One end of the fourth capacitor is connected with the third clock signal end, and the other end of the fourth capacitor is connected with a fourth terminal; the source electrode of the fifth NMOS tube is connected with the middle voltage source end, the drain electrode of the fifth NMOS tube is connected with the fourth terminal, and the grid electrode of the fifth NMOS tube is connected with the fifth terminal; The source electrode of the fifth PMOS tube is connected with the sixth terminal, the drain electrode of the fifth PMOS tube is connected with the fourth terminal, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with the sixth terminal, the drain electrode of the sixth PMOS tube is connected with the second terminal, and the grid electrode of the sixth PMOS tube is connected with the fourth terminal.
6. The charge pump as recited in claim 5, wherein in said first stage charge pump module, When the first clock signal input by the negative electrode of the second capacitor is at a low level and the fourth clock signal input by the negative electrode of the third capacitor is at a high level, the voltage of the second terminal is at a high voltage, the third NMOS tube is conducted, and the voltage of the second terminal is Wherein, the method comprises the steps of, Represents the threshold voltage of the third NMOS transistor, Representing the voltage of the second terminal; When the first clock signal input by the negative electrode of the second capacitor is at a high level and the fourth clock signal input by the negative electrode of the third capacitor is at a low level, the voltage of the second terminal is as follows: ; When the node voltage of the second terminal is high level and the node voltage of the fourth terminal is low level, the sixth PMOS tube is opened, the fifth PMOS tube is closed, and the voltage of the sixth terminal is as follows: wherein, the method comprises the steps of, Representing a voltage of the sixth terminal; when the node voltage of the second terminal is low level and the node voltage of the fourth terminal is high level, the sixth PMOS tube is closed, the fifth PMOS tube is opened, and the voltage of the sixth terminal is as follows: 。
7. the charge pump of claim 5, wherein the first clock signal and the second clock signal of the oscillator are the same clock and the third clock signal and the fourth clock signal of the oscillator are complementary.
8. The charge pump of claim 5, wherein the second stage charge pump module comprises a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third zener diode, a fourth zener diode, a fifth zener diode, a sixth zener diode, and a seventh zener diode; The source electrode of the eighth NMOS tube is connected with the sixth terminal, the drain electrode of the seventh NMOS tube is connected with the seventh terminal, the grid electrode of the seventh NMOS tube is connected with the eighth terminal, the positive electrode of the third Zener diode is connected with the second clock signal end, the negative electrode of the third Zener diode is connected with the seventh terminal, one end of the seventh capacitor is connected with the third clock signal end, the other end of the seventh capacitor is connected with the eighth terminal; The source electrode of the ninth NMOS tube is connected with a sixth terminal, the drain electrode of the ninth NMOS tube is connected with the ninth terminal, the grid electrode of the fifth Zener diode is connected with the first clock signal end, the cathode of the fifth Zener diode is connected with the ninth terminal, one end of the ninth capacitor is connected with the fourth clock signal end, the other end of the ninth capacitor is connected with the tenth terminal, the source electrode of the tenth NMOS tube is connected with the sixth terminal, the drain electrode of the tenth NMOS tube is connected with the tenth terminal, the grid electrode of the sixth Zener diode is connected with the ninth terminal, and the anode of the sixth Zener diode is connected with the fourth clock signal end; The source electrode of the seventh PMOS tube is connected with a target output end of the charge pump, the drain electrode of the seventh PMOS tube is connected with a ninth terminal, the grid electrode of the eighth PMOS tube is connected with the drain electrode of the eighth PMOS tube, the source electrode of the eighth PMOS tube is connected with the VCP end, the drain electrode of the eighth PMOS tube is connected with the eighth terminal, the grid electrode of the eighth PMOS tube is connected with the ninth terminal, one end of the tenth capacitor is connected with an intermediate voltage source end, the other end of the tenth capacitor is connected with the target output end of the charge pump, the positive electrode of the seventh Zener diode is connected with the intermediate voltage source end, the negative electrode of the seventh Zener diode is connected with the target output end of the charge pump, and the target output end of the charge pump is used for outputting the amplified intermediate voltage to the high-side power tube.
9. The charge pump as recited in claim 8, wherein in said second stage charge pump module, When the third clock signal is inputted to the negative electrode of the seventh capacitor and the second clock signal is inputted to the negative electrode of the sixth capacitor and the second clock signal is inputted to the high level, the voltage of the seventh terminal is high, and the eighth NMOS tube is turned on, and the voltage of the eighth terminal is Wherein, the method comprises the steps of, Represents the voltage of the eighth terminal, Representing the threshold voltage of the eighth NMOS transistor; When the negative electrode of the seventh capacitor inputs the third clock signal to be at a high level and the negative electrode of the sixth capacitor inputs the second clock signal to be at a low level, the voltage of the eighth terminal is: ; when the voltage of the eighth terminal is high voltage and the voltage of the ninth terminal is low voltage, the eighth PMOS tube is opened, the seventh PMOS tube is closed, and the voltage of the target output end of the charge pump is as follows: , wherein, Representing the voltage at the target output of the charge pump; When the voltage of the eighth terminal is low and the voltage of the ninth terminal is high, the eighth PMOS tube is closed, the seventh PMOS tube is opened, and the voltage of the target output end of the charge pump is as follows: 。
10. The charge pump of claim 8, wherein the third zener diode is configured to limit the voltage difference across a sixth capacitance, the fourth zener diode is configured to limit the voltage difference across a seventh capacitance, the fifth zener diode is configured to limit the voltage difference across an eighth capacitance, the sixth zener diode is configured to limit the voltage difference across a ninth capacitance, the seventh zener diode is configured to limit an upper voltage limit of a charge pump target output, and the tenth capacitance is configured to stabilize the voltage of the charge pump target output.

Description

Charge pump Technical Field The invention relates to the technical field of charge pump driving, in particular to a charge pump. Background Currently, for the main brush motor chip, a charge pump structure as shown in fig. 1 is mostly adopted as a built-in charge pump, and a gate voltage for controlling the on and off of the high-side power tube of the H bridge is generated. The method comprises the steps of setting an oscillator in a brush motor driving chip, outputting a clock signal as a clock source of a charge pump, setting a low dropout linear regulator LDO, outputting voltage VDD_VCP as a boost value of the charge pump, and generally, setting the starting voltage of a grid electrode of a high-side power tube of an H bridge to be higher than the power voltage by 5V so as to ensure that the internal resistance of the high-side power tube is minimum under the condition of normal operation and improve the motor driving performance, wherein the setting of the output voltage of the charge pump is as follows: . However, such an adaptive charge pump requires a certain minimum value of the power supply voltage, and cannot operate normally at a low operating voltage. In view of this, there is a need for a more advanced charge pump to solve the problem that the charge pump in the prior art cannot generate the operating voltage required by the high-side power tube at the low operating voltage. Disclosure of Invention The invention aims to provide a charge pump, in particular to a charge pump structure suitable for a low-voltage brushed chip, which can normally output the voltage required by a grid electrode of a high-side power tube under a lower working voltage and solves the problem that the charge pump in the prior art cannot generate the working voltage required by the high-side power tube under the low working voltage. In order to achieve the above object, the present invention provides the following technical solutions: In a first aspect, the present invention provides a charge pump, which may comprise: the system comprises a level processing module, an oscillator and a multi-stage charge pump module; The level processing module is connected with the oscillator, and the oscillator is connected with the multi-stage charge pump module; The level processing module is used for generating a target voltage, and inputting the target voltage into the oscillator, wherein the target voltage is larger than or equal to the ground level and smaller than the power supply voltage; The oscillator is used for taking the target voltage as a ground level, taking an intermediate voltage as a high level to generate a target clock signal, and inputting the target clock signal to the multi-stage charge pump module, wherein the intermediate voltage is a secondary voltage generated after the power supply voltage is subjected to on-chip or off-chip voltage stabilization; The multistage charge pump is used for amplifying the intermediate voltage in multiple stages based on the target clock signal and outputting the intermediate voltage to the high-side power tube. Preferably, the level processing module may include a current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a first zener diode, and a second zener diode, where the fourth PMOS transistor, the first NMOS transistor, and the second NMOS transistor are high-voltage power MOS transistors; The source electrode of the first PMOS tube is connected with the power supply end, the grid electrode of the second PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the power supply end, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube is respectively connected with the drain electrode and the grid electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the second NMOS tube is respectively connected with the drain electrode and the grid electrode of the third PMOS tube, and the source electrode of the second NMOS tube is grounded; The grid electrode of the third PMOS tube is connected with a first terminal, the drain electrode of the fourth PMOS tube is grounded, the source electrode of the fourth PMOS tube is connected with the output end of the level processing module, the grid electrode of the fourth PMOS tube is connected with the first terminal, one end of the first resistor is connected with the middle voltage source end, the other end of the first resistor is connected with one end of the second resistor, the other end of the second