Search

CN-122001189-A - Feedback-free Buck converter loop and control method

CN122001189ACN 122001189 ACN122001189 ACN 122001189ACN-122001189-A

Abstract

The invention discloses a feedback-free Buck converter loop and a control method, which can solve the problem of excessively high precision requirement of a digital-to-analog converter, eliminate precision loss and stability risks introduced by a feedback network, break through contradiction between micro-step adjustment and system complexity, and remarkably reduce the system complexity and cost. The loop comprises a reference voltage adjusting module and a digital interface, the reference voltage adjusting module and the digital interface are connected with a digital-to-analog converter, the digital-to-analog converter is connected with an error amplifier, the error amplifier is connected with a SUMN input end of a PWM comparison module, an output end of the digital-to-analog converter is also sequentially connected with a first resistor and a second resistor, a voltage dividing point between the first resistor and the second resistor is connected with a SUMN input end of the PWM comparison module, the PWM comparison module is connected with a LOGIC/POWER module, the LOGIC/POWER module is connected with an inductor, the inductor is connected with a SUMP input end of the error amplifier and the PWM comparison module, a SW acquisition point between the LOGIC/POWER module and the inductor is connected with a ramp generator, and the ramp generator is connected with a SUMP input end of the PWM comparison module.

Inventors

  • XUE RUONAN
  • XIA QIN
  • ZHANG XI
  • LU YAN

Assignees

  • 陕西亚成微电子股份有限公司

Dates

Publication Date
20260508
Application Date
20251231

Claims (10)

  1. 1. The feedback-free Buck converter loop is characterized by comprising a reference voltage adjusting module and a digital interface, wherein the reference voltage adjusting module and the output end of the digital interface are connected with a digital-to-analog converter DAC, the reference voltage adjusting module is used for controlling the digital-to-analog converter DAC to generate reference voltage controlled by the digital interface, the output end of the digital-to-analog converter DAC is connected with the reference voltage input end of an error amplifier EA, the output end of the error amplifier EA is connected to the SUMN input end of a PWM comparison module after filtering, the output end of the digital-to-analog converter DAC is also sequentially connected with a first resistor R1 and a second resistor R2, a voltage dividing point between the first resistor R1 and the second resistor R2 is connected to the SUMN input end of the PWM comparison module, the output end of the PWM comparison module is connected with a LOGIC/POWER module, the output end of the LOGIC/POWER module is connected with an inductor L, the output end of the inductor L is connected with the output voltage input end of the error amplifier EA and the SUMP input end of the PWM comparison module after filtering, and the ramp wave is connected with the PWM comparison module.
  2. 2. The feedback-free Buck converter loop of claim 1, wherein the reference voltage regulation module includes a bandgap voltage source BG and a linear regulator LDO connected, an output terminal of the linear regulator LDO is connected to the digital-to-analog converter DAC, the bandgap voltage source BG is used for generating a reference voltage source, and the linear regulator LDO is used for boosting a VBG voltage output by the bandgap voltage source BG to a set value.
  3. 3. The feedback-free Buck converter loop according to claim 2, wherein the output voltage VOUT at the output end of the inductor L is 0.6V-1.23V, the reference voltage VREF output by the DAC is 0.6V-1.23V, the VBG voltage output by the bandgap voltage source BG is 1.2V at maximum, and the linear regulator LDO boosts the VBG voltage to 1.23V at maximum.
  4. 4. A feedback-free Buck converter loop according to claim 3, wherein the digital interface includes an MIPI interface or an I2C interface.
  5. 5. The feedback-free Buck converter Loop of claim 4 wherein the code value of the digital interface controls the divider resistance of the DAC to achieve that the reference voltage VREF output by the DAC increases by 10mv for every increase in the code value, the expression corresponding to the output voltage VOUT is VOUT=0.6V+D <0:5 >. 10mv, and D <0:5> represents a 6-bit binary digital input.
  6. 6. A feedback-free Buck converter loop according to claim 1, wherein the digital-to-analog converter DAC employs a segmented resistive architecture with DNL < ±0.5LSB at 10mV steps.
  7. 7. A feedback-free Buck converter loop according to claim 1, wherein the output stage of the digital-to-analogue converter DAC is provided with a buffer, the slew rate of the buffer being >1V/μs.
  8. 8. A feedback-free Buck converter loop according to claim 1, wherein the input of the error amplifier EA is connected to an RC filter which uses RC low pass filtering with a cut-off frequency fc >10 x switching frequency.
  9. 9. A control method of a feedback-free Buck converter loop is characterized by adopting the feedback-free Buck converter loop in any one of claims 1 to 7, comprising the steps of controlling a digital-to-analog converter DAC to generate a reference voltage VREF controlled by a digital interface by a reference voltage adjusting module, amplifying errors of the reference voltage VREF and an output voltage VOUT by an error amplifier EA to generate vea signals, dividing the error amplifier EA and then superposing the divided voltage VRFEF _DIV of the reference voltage VREF by vea signals to form SUMN input signals of a PWM comparison module, generating ramp signals by a ramp generator by the collected SW signals, superposing the ramp signals to the output voltage VOUT to form SUMP input signals of the PWM comparison module, comparing SUMN input signals with SUMP input signals by the PWM comparison module, and controlling on and off of a switching tube to realize loop control.
  10. 10. The control method of the feedback-free Buck converter loop according to claim 9, wherein the output voltage VOUT is 0.6V-1.23V, the reference voltage regulating module comprises a band gap voltage source BG and a linear voltage regulator LDO which are connected, the VBG voltage output by the band gap voltage source BG is 1.2V at maximum, the linear voltage regulator LDO boosts the VBG voltage to 1.23V at maximum, so that the reference voltage VREF output by the digital-to-analog converter DAC is controlled to be 0.6V-1.23V, the code value of the digital interface controls the voltage dividing resistance of the digital-to-analog converter DAC, the reference voltage VREF output by the digital-to-analog converter DAC is increased by 10mv when the code value is increased by one bit, and the expression corresponding to the output voltage VOUT is VOUT=0.6V+D <0:5 >. 10mv, and D <0:5> represents a 6-bit binary number input.

Description

Feedback-free Buck converter loop and control method Technical Field The invention relates to the technical field of switching power supply control, in particular to a feedback-free Buck converter loop and a control method. Background In the conventional Buck converter design, the regulation of the output voltage generally relies on a resistor divider feedback network (formed by resistors R1 and R2) to divide the output voltage into a feedback voltage, which is compared with a fixed reference voltage at the input of an error amplifier, and then the duty cycle is adjusted by a PWM modulator to achieve voltage regulation. When the output voltage needs to be regulated through a digital interface, the conventional scheme dynamically regulates the reference voltage of the error amplifier through a digital-to-analog converter, but the prior art has the following core defects: the feedback network introduces precision loss, namely the precision deviation (typical value +/-1%) of the divider resistor and the temperature drift can lead to the deviation of the feedback voltage and the actual output voltage, and the output precision is directly influenced; the step length of the digital-to-analog converter is strictly required, if the target output voltage regulation step length is DeltaV (such as 10 mV), the required step length DeltaVDAC of the digital-to-analog converter is required to meet the relation that DeltaVDAC=DeltaV× (R2/(R1+R2)), and when the voltage division ratio is 0.5, the step length of the output voltage of 10mV is required to be only 5mV; The design bottleneck of the digital-to-analog converter is that the resolution, linearity and temperature drift index of the 5 mV-level micro-step digital-to-analog converter are very high, and a high-precision digital-to-analog converter with more than 12 bits is adopted, so that the cost of a chip and the design complexity are obviously increased; The loop compensation burden is that the feedback network introduces extra poles/zeros, and the extra poles/zeros are needed to be offset through the Type II/III compensation network, so that the design difficulty and the layout area are increased; noise sensitivity problem, that is, feedback wiring is easy to be interfered by switching noise, and isolation measures are required to be strictly laid out. In order to solve the problems, the prior art generally adopts two schemes, namely a high-precision digital-to-analog converter scheme, namely a scheme of generating a micro-step reference voltage by using more than 12-bit digital-to-analog converters, but with high cost, large power consumption, weak noise immunity and other bottlenecks, and a precision resistor scheme, namely a scheme of adopting 0.1% precision resistor to reduce the voltage dividing error, but cannot solve the problem of digital-to-analog converter step compression, and the resistance temperature drift still affects the long-term stability. The existing architecture has irreconcilable contradiction, namely firstly, the contradiction between precision and cost, the conflict between the micro-step requirement and the precision limit of the digital-to-analog converter/resistor, secondly, the design of the compensation network and the noise resistance requirement can increase the system cost, and finally, the contradiction between stability and the feedback network can maintain the loop stability by complex compensation. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a loop of a feedback-free Buck converter and a control method, which can solve the problem of excessively high precision requirement of a digital-to-analog converter, eliminate the precision loss and stability risks introduced by a feedback network, break through the contradiction between micro-step adjustment and system complexity, and remarkably reduce the system complexity and cost. In order to achieve the above objective, in one aspect, the present invention provides a feedback-free Buck converter loop, including a reference voltage adjusting module and a digital interface, where output ends of the reference voltage adjusting module and the digital interface are connected to a digital-to-analog converter DAC, the reference voltage adjusting module is used to control the digital-to-analog converter DAC to generate a reference voltage controlled by the digital interface, an output end of the digital-to-analog converter DAC is connected to a reference voltage input end of an error amplifier EA, an output end of the error amplifier EA is connected to an input end of a DAC SUMN of a PWM comparison module after filtering, an output end of the digital-to-analog converter DAC is further connected to a first resistor R1 and a second resistor R2 in sequence, a voltage dividing point between the first resistor R1 and the second resistor R2 is connected to an SUMN input end of the PWM comparison module, an output end of the PWM comparison module is c