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CN-122001205-A - Apparatus and method for adaptively adjusting dead time in half-bridge circuit and application thereof

CN122001205ACN 122001205 ACN122001205 ACN 122001205ACN-122001205-A

Abstract

The invention relates to an apparatus and a method for adaptively adjusting dead time in a half-bridge circuit. The invention also relates to a circuit for carrying out said method, to the use of said method in a DC-DC converter or inverter and to the use of said method in an energy converter or in a high-side switch and a low-side switch for commutating a current.

Inventors

  • ZHAO HONGMING
  • J. JULES

Assignees

  • 罗伯特·博世有限公司

Dates

Publication Date
20260508
Application Date
20251107
Priority Date
20241107

Claims (10)

  1. 1. A method for adaptively adjusting dead time in a half-bridge circuit consisting of a high-side MOSFET (HS) and a low-side MOSFET (LS), characterized in that, Detecting a gate-source voltage (Vgs) of the low-side MOSFET (LS) or the high-side MOSFET and a current change (di/dt) of a parasitic source inductance flowing through the MOSFETs to identify an on-process and an off-process of the HS-MOSFET and the LS-MOSFET; based on these detected signals, the dead time (Td 1, td 2) is dynamically adjusted in each switching cycle using a predictive algorithm, wherein the dead time is iteratively adjusted to reach an optimal point that prevents switching process overlap and minimizes switching losses.
  2. 2. The method of claim 1, wherein the step of determining the position of the substrate comprises, The delay between turning off the high-side MOSFET and turning on the low-side MOSFET is referred to as dead time Td1, and the dead time is adjusted by a predictive algorithm based on the detected current change (di/dt) and the gate-source voltage (Vgs); if the dead time is too long, the dead time interval for the next switching cycle is reduced by one step, and if the dead time is too short, the dead time interval is increased by one step.
  3. 3. The method of claim 2, wherein the step of determining the position of the substrate comprises, The delay between turning off the low-side MOSFET and turning on the high-side MOSFET is referred to as dead time Td2, and the dead time is also adjusted in each switching cycle by a predictive algorithm.
  4. 4. A method according to any one of claim 1 to 3, wherein, Two comparators, one positive di/dt comparator (comp_ didt _pos) and one negative di/dt comparator (comp_ didt _neg), are used to monitor the rate of current change during the switching process and are used to adjust the dead times Td1 and Td2.
  5. 5. The method according to any one of claim 1 to 4, wherein, Dead time adjustment is used in applications with silicon carbide (SiC) MOSFETs or gallium nitride (GaN) MOSFETs to minimize switching losses or reduce or avoid overshoot and undershoot and ringing.
  6. 6. The method according to any one of claim 1 to 5, wherein, The method is used in a step-up or step-down direct current converter (DC-DC converter) or inverter or in a high-side switch and a low-side switch for commutating a current, wherein the same principle for adjusting the dead time is applied to both switches.
  7. 7. The method according to any one of claim 1 to 6, wherein, Dead time control takes place in consideration of various operating conditions, such as load current, temperature and device variations, without the need for additional high voltage capable components.
  8. 8. A circuit for performing the method of any one of claims 1 to 7.
  9. 9. Use of the method according to any of claims 1 to 7 in a DC-DC converter or inverter for minimizing switching losses and optimizing dead time in SiC or GaN based power semiconductors.
  10. 10. Use of a method according to any of claims 1 to 7 in energy converters or high-side and low-side switches for commutating currents for reducing or avoiding overshoot and undershoot and disturbances.

Description

Apparatus and method for adaptively adjusting dead time in half-bridge circuit and application thereof Technical Field The present invention relates to an apparatus and method for adaptively adjusting dead time in a half-bridge circuit. Background In standard half-bridge circuits commonly used in inverters and converters, the introduction of dead time is critical to prevent cross-conduction or simultaneous conduction (even partial conduction) of the high-side and low-side MOSFETs. Without such delay, there is a risk of short circuits or overloads that may damage the components. Dead time, however, is a sensitive problem in that if the dead time is too long, additional energy loss occurs due to diode conduction, reverse recovery, or non-zero voltage switching effects. It is therefore important to optimally adjust the dead time to find a proper balance between safety and efficiency. In literature and practice, there are various schemes for optimizing dead time. Traditionally, many of these methods are based on direct detection of the switching node. For example Maderbacher et al have studied a method in which the body diode turn-on is identified by detecting a negative voltage spike on the switch node. Similarly, niwa et al propose to integrate SenseFoets within the power module to detect diode commutation [1, 2]. However, both of these schemes require additional components and are limited by propagation delay, which may impair their efficiency. Other schemes, such as those proposed by Vahid and Dragan, propose a sensorless scheme that uses feedback of the load voltage to determine the optimal dead time based on the minimum duty cycle [3]. While this approach is efficient for voltage converters, it is premised on fast computational power and is not suitable for all applications. Texas instruments (Texas Instruments) developed a predictive control method based on detection of gate-source voltage (Vgs) and drain-source voltage (Vds) of low-side MOSFETs as described in the application report of UCC27221/UCC27222 [4]. However, this solution has limitations in that it requires access to components that are resistant to high pressures, which increases design complexity and cost, especially in automotive applications. However, because both of these approaches require access to the switching node or drain-source side, they present significant challenges in terms of design complexity, cost, and on-chip integration in automotive applications due to the high voltage capable components required. Accordingly, a predictive dead time control scheme based on low voltage information (LV) about the gate driver (steering and diagnostics) is presented herein. By utilizing Vgs of either the low side MOSFET or the high side MOSFET and associated parasitic elements in the circuit, dead time can be adjusted accurately and without direct access to the high voltage region. This reduces design complexity and enables easier integration into systems relying on cost-effective, highly integrated solutions, as is often required in the automotive industry. [1] Niwa, A. Et al (2018). "Dead Time control gate driver (adead-Time-Controlled GATE DRIVER Using Current-SENSE FET INTEGRATED IN SIC MOSFET) Using a Current-detecting FET integrated in a SiC MOSFET". IEEE Power electronics journal, 33 (4), pages 3258-3267. [2] Maderbacher, g., jackum, t., pribyl, w., wassermann, m., petschar, a., & Sandner, c. (2011). "automatic dead time optimization in high frequency DC-DC buck converter in 65nm CMOS". In 2011, ESSCIRC, conference Edition (ESSCIRC), helsinki, finland, pages 487-490. [3] Yousefzadeh, v. & Maksimovic, d. (2006). Sensorless optimization of dead time in dc voltage converters with synchronous rectifiers. IEEE Power electronics journal, 21 (4), pages 994-1002. [4] S. Mappus, "predictive gate drive TM boost synchronous DC/DC power converter efficiency (PREDICTIVE GATE DRIVETM Boosts Synchronous DC/DC Power Converter Efficiency)", texas instruments application report, month 4 of SLUA281,2003. DE 11 2017 006 120 B4 relates to a circuit arranged in a half-bridge topology, comprising a high-side transistor and a low-side transistor, which have a source, a drain and a gate, respectively, wherein the source of the high-side transistor and the drain of the low-side transistor are electrically connected at a first node, a gate driver electrically connected to the gate of the high-side transistor, a bootstrap capacitor electrically connected in parallel with the gate driver, a shunt diode having a cathode and an anode, wherein the cathode of the shunt diode is connected to the capacitor at a second node and the anode of the shunt diode is connected to ground, wherein the shunt diode provides a charging path with a low voltage drop for charging the bootstrap capacitor, and a shunt resistor electrically connected between the first node and the second node, such that the shunt diode is decoupled from the first node and the current flowing through the shu