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CN-122001206-A - Automatic dead zone control circuit and LLC resonant converter

CN122001206ACN 122001206 ACN122001206 ACN 122001206ACN-122001206-A

Abstract

The application relates to the technical field of circuit control, in particular to an automatic dead zone control circuit and an LLC resonant converter. The circuit comprises a maximum dead zone control circuit, a narrow pulse generating circuit, a level shift high-voltage tube driving and dead zone detection input circuit, a level shift and comparison circuit and a dead zone control logic circuit. The dead time of the high-side driving signal and the low-side driving signal is dynamically adjusted based on the clock input signal and the dead time state detected in real time, so that automatic dead time control of the LLC resonant converter switching tube is realized, the through phenomenon is effectively avoided, the efficiency and the reliability of the converter are improved, the dependence on external high-voltage capacitance is reduced, and the cost and the complexity of the system are further reduced.

Inventors

  • Shen Renbo

Assignees

  • 浙江屹晶微电子股份有限公司

Dates

Publication Date
20260508
Application Date
20260121

Claims (10)

  1. 1. An automatic dead zone control circuit, comprising: a maximum dead zone control circuit (10) for generating a high-side dead zone control signal H1 and a low-side dead zone control signal L1 based on a clock input signal CLKin; a narrow pulse generating circuit (20) provided after the maximum dead zone control circuit (10) for generating a rising edge narrow pulse signal Hon1 and a falling edge narrow pulse signal Hoff1 based on the high-side drive signal H2; the level shift high-voltage tube driving and dead zone detection input circuit (30) is connected with the narrow pulse generating circuit (20) and is used for generating a high-side high-voltage tube opening signal Hon and a dead zone detection signal H3 based on the rising edge narrow pulse signal Hon1 and generating a high-side high-voltage tube closing signal Hoff based on the falling edge narrow pulse signal Hoff 1; the level shift and comparison circuit (40) is connected with the level shift high-voltage tube driving and dead zone detection input circuit (30) and is used for generating a high-side dead zone comparison signal H4 and a low-side dead zone comparison signal H5 based on the dead zone detection signal H3; The dead zone control logic circuit comprises a dead zone signal generation module (51) and a logic combination module (52), wherein the dead zone signal generation module (51) is connected with the level shift and comparison circuit (40) and is used for generating a high-side dead zone signal DTH based on the high-side dead zone comparison signal H4 and a low-side dead zone signal DTL based on the low-side dead zone comparison signal H5, and the logic combination module (52) is arranged between the maximum dead zone control circuit (10) and the narrow pulse generation circuit (20) and is connected with the dead zone signal generation module (51) and is used for generating a high-side driving signal H2 based on the high-side dead zone control signal H1 and the high Bian Siou signal DTH and generating a low-side driving signal L2 based on the low-side dead zone control signal L1 and the low-side dead zone signal DTL.
  2. 2. The automatic dead band control circuit of claim 1, wherein the maximum dead band control circuit (10) includes a high-side delay path for generating the high-side dead band control signal H1 and a low-side delay path for generating the low-side dead band control signal L1.
  3. 3. The automatic dead zone control circuit of claim 2, wherein the high-side delay path comprises a second inverter U2, a fifth inverter U5, a sixth inverter U6, a second PMOS transistor P2, a fourth NMOS transistor N4, a sixth resistor R6, and a fifth capacitor C5, wherein an input terminal of the second inverter U2 is configured to receive the clock input signal CLKin, and the second inverter U2 outputs a clock inversion signal CLKinn to a gate of the second PMOS transistor P2 and a gate of the fourth NMOS transistor N4, wherein a source of the second PMOS transistor P2 is connected to a power supply terminal VDD, a drain of the second PMOS transistor P2 is connected to a first terminal of the sixth resistor R6, a source of the fourth NMOS transistor N4 is connected to a ground terminal GND, a drain of the fourth NMOS transistor N4 is connected to a second terminal of the sixth resistor R6, a fifth terminal of the fifth capacitor C5 is connected to a gate of the second PMOS transistor P2 and a gate of the fourth NMOS transistor N4, a source of the second PMOS transistor P2 is connected to a fifth terminal of the fifth NMOS transistor P5 is connected to a fifth terminal of the fifth NMOS transistor N5, and a dead zone signal is connected to the fifth capacitor C5, and the output terminal of the fifth NMOS transistor N4 is connected to the fifth inverter U5 is connected to the fifth terminal of the fifth inverter U6; The low-side delay path comprises an eighth PMOS tube P8, a ninth NMOS tube N9, a ninth resistor R9, a sixth capacitor C6, a thirteenth inverter U13 and a fourteenth inverter U14, wherein the grid electrode of the eighth PMOS tube P8 and the grid electrode of the ninth NMOS tube N9 are used for receiving a clock input signal CLKin, the source electrode of the eighth PMOS tube P8 is connected to a power supply end VDD, the drain electrode of the eighth PMOS tube P8 is connected to the first end of the ninth resistor R9, the source electrode of the ninth NMOS tube N9 is connected to a ground end GND, the drain electrode of the ninth NMOS tube N9 is connected to the second end of the ninth resistor R9, the first end of the sixth capacitor C6 is connected to the second end of the ninth resistor R9, the second end of the sixth capacitor C6 is connected to the ground end GND, a node voltage signal at the first end of the sixth capacitor C6 is input to the thirteenth inverter U13, the drain electrode of the thirteenth inverter U13 is connected to the output end of the thirteenth inverter U14 is connected to the dead zone of the output end of the fourteenth inverter U1.
  4. 4. The automatic dead zone control circuit according to claim 1, wherein the narrow pulse generating circuit (20) includes a falling edge narrow pulse generating path for generating the falling edge narrow pulse signal Hon1 and a falling edge narrow pulse generating path for generating the falling edge narrow pulse signal Hoff1.
  5. 5. The automatic dead zone control circuit of claim 4, wherein the falling edge narrow pulse generation path comprises a first inverter U1, an eighth inverter U8, an eleventh inverter U11, a first PMOS transistor P1, a third NMOS transistor N3, a fifth resistor R5, a fourth capacitor C4, and a third and gate U3, wherein an input terminal of the eighth inverter U8 is configured to receive the high-side driving signal H2, an output terminal of the eighth inverter U8 is connected to an input terminal of the eleventh inverter U11, a gate of the first PMOS transistor P1, and a gate of the third NMOS transistor N3, a source of the first PMOS transistor P1 is connected to a power supply VDD terminal, a drain of the first PMOS transistor P1 is connected to a first terminal of the fifth resistor R5, a source of the third NMOS transistor N3 is connected to ground GND, a drain of the third NMOS transistor N3 is connected to the fifth resistor R5, an output terminal of the fourth NMOS transistor U8 is connected to an input terminal of the fourth PMOS transistor U1, a gate of the third NMOS transistor N3 is connected to a third input terminal of the fourth PMOS transistor N1, a drain of the third NMOS transistor N3 is connected to a first terminal of the fifth resistor R5, a drain of the third NMOS transistor N3 is connected to a first terminal of the third NMOS transistor N3, and a gate of the third NMOS transistor N3 is connected to a third input terminal of the fourth PMOS transistor N3; The falling edge narrow pulse generation path comprises a twenty-first inverter U21, a sixteenth inverter U16, a ninth PMOS tube P9, a tenth NMOS tube N10, a tenth resistor R10 and a seventeenth AND gate U17, wherein the twenty-first inverter U21, the grid of the ninth PMOS tube P9 and the grid of the tenth NMOS tube N10 are used for receiving a high-side driving signal H2, the source electrode of the ninth PMOS tube P9 is connected to a power supply end VDD, the drain electrode of the ninth PMOS tube P9 is connected to a first end of the tenth resistor R10, the source electrode of the tenth NMOS tube N10 is connected to a ground end GND, the drain electrode of the tenth NMOS tube N10 is connected to a second end of the tenth resistor R10, the first end of the seventh capacitor C7 is connected to a second end GND, the second end of the seventh capacitor C7 is connected to a ground end GND, the voltage node of the first end of the seventh capacitor C7 is connected to the sixteenth end of the sixteenth inverter U16, the drain electrode of the sixteenth NMOS tube N10 is connected to the second end of the seventeenth AND gate U17, and the sixteenth end of the seventeenth capacitor C7 is connected to the seventeenth end of the seventeenth gate 17.
  6. 6. The automatic dead zone control circuit according to claim 1, wherein the level shift high voltage tube driving and dead zone detection input circuit (30) includes a fourth inverter U4, an eighteenth inverter U18, a third PMOS tube P3, a tenth PMOS tube P10, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, an eleventh NMOS tube N11, a seventh resistor R7, a seventh diode D7, and an eighth diode D8; the input end of the fourth inverter U4 is configured to receive a rising edge narrow pulse signal Hon1, the output end of the fourth inverter U4 is connected to the gate of the third PMOS transistor P3 and the gate of the fifth NMOS transistor N5, the source of the third PMOS transistor P3 is connected to the power supply end VDD, the drain of the third PMOS transistor P3 is connected to the first end of the seventh resistor R7, the source of the fifth NMOS transistor N5 is connected to the ground end GND, the drain of the fifth NMOS transistor N5 is connected to the second end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the output end of the high-side high-voltage transistor on signal Hon, the gate of the sixth NMOS transistor N6 is connected to the output end of the fourth inverter U4, the source of the sixth NMOS transistor N6 is connected to the ground end GND, the drain of the sixth NMOS transistor N6 is connected to the high-side of the seventh diode D7, the drain of the seventh NMOS transistor N6 is connected to the high-side high-voltage transistor on signal Hon 7 is connected to the output end of the eighth NMOS transistor N8, the drain of the seventh NMOS transistor N6 is connected to the high-side high-voltage transistor on signal Hon is connected to the output end of the eighth NMOS transistor N8, the output end of the eighth NMOS transistor N7 is connected to the high-side of the output end of the high-voltage transistor N8 is connected to the output end of the eighth NMOS transistor N7, the drain electrode of the seventh NMOS transistor N7 is connected to the output end of the high-side high-voltage transistor turn-on signal Hon, the grid electrode of the eighth NMOS transistor N8 is used for receiving the rising edge narrow pulse signal Hon1, the source electrode of the eighth NMOS transistor N8 is connected to the ground end GND, the drain electrode of the eighth NMOS transistor N8 is connected to the output end of the dead zone detection signal H3, the input end of the eighteenth inverter U18 is used for receiving the falling edge narrow pulse signal Hoff1, the output end of the eighteenth inverter U18 is connected to the grid electrode of the tenth PMOS transistor P10 and the grid electrode of the eleventh NMOS transistor N11, the source electrode of the tenth PMOS transistor P10 is connected to the power end VDD, the drain electrode of the tenth NMOS transistor P10 is connected to the output end of the high-side high-voltage transistor turn-off signal Hoff, the source electrode of the eleventh NMOS transistor N11 is connected to the ground end GND, and the drain electrode of the eleventh NMOS transistor N11 is connected to the output end of the high-side high-voltage transistor turn-off signal Hoff.
  7. 7. The automatic dead zone control circuit according to claim 1, wherein the level shift and comparison circuit (40) includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, an eighth resistor R8, an eleventh resistor R11, a twelfth resistor R12, a tenth comparator U10, and a 20 th comparator U20; the source of the fourth PMOS tube P4 and the source of the fifth PMOS tube P5 are connected to a power supply end VDD, the grid of the fourth PMOS tube P4 and the grid of the fifth PMOS tube P5 are both used for being connected to a bias voltage VBP, the drain of the fourth PMOS tube P4 is connected to the first end of the eighth resistor R8 and the inverting input end of the tenth comparator U10, the drain of the fifth PMOS tube P5 is connected to the positive input end of the tenth comparator U10 and the source of the seventh PMOS tube P7, the output end of the tenth comparator U10 is used for outputting a high-side dead zone comparison signal H4, the source of the sixth PMOS tube is connected to the second end of the eighth resistor R8, the source of the seventh PMOS tube P7 is connected to the drain of the fifth PMOS tube P5, the grid of the sixth PMOS tube P7 is used for receiving the dead zone detection signal H3, the drain of the seventh PMOS tube P7 is connected to the positive input end of the seventh PMOS tube U10 and the source of the seventh PMOS tube P7, the output end of the tenth comparator P10 is used for outputting a high-side dead zone comparison signal H4, the source of the seventh PMOS tube P7 is connected to the drain of the eighth resistor R8, the drain of the seventh PMOS tube P7 is connected to the drain of the eleventh PMOS tube P11, and the drain of the eleventh tube P11 is connected to the drain of the eleventh tube P11, and the drain tube P11 is connected to the drain of the eleventh tube P11 is connected together, and the drain tube P11 is connected to the drain of the drain tube P, the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are both connected to the bias voltage VBP, the drain electrode of the eleventh PMOS transistor P12 is connected to the ground through the eleventh resistor R11, the drain electrode of the twelfth PMOS transistor P12 is connected to the non-inverting input terminal of the twenty-first comparator U20 and the source electrode of the fourteenth PMOS transistor P14, the drain electrode of the thirteenth PMOS transistor P13 is connected to the inverting input terminal of the twenty-first comparator U20 and the first terminal of the twelfth resistor R12, the output terminal of the twenty-first comparator U20 is used for outputting the low-side dead zone comparison signal H5, the gate electrode of the fourteenth PMOS transistor P14 is used for receiving the dead zone detection signal H3, the drain electrode of the fourteenth PMOS transistor P14 is connected to the ground, the source electrode of the fifteenth PMOS transistor P15 is connected to the second terminal of the twelfth resistor R12, and the gate electrode and the drain electrode of the fifteenth PMOS transistor P15 are connected to the ground.
  8. 8. The automatic dead zone control circuit of claim 1, wherein the dead zone signal generation module (51) comprises a ninth inverter U9, a nineteenth inverter U19, a twelfth D flip-flop, and a twelfth D flip-flop, wherein an input of the ninth inverter U9 receives the high side dead zone comparison signal H4, an output of the ninth inverter U9 is connected to a CP input of the twelfth D flip-flop U12, an RN input of the twelfth D flip-flop U12 is configured to receive the clock input signal CLKin, a D input of the twelfth D flip-flop U12 is connected to the power supply terminal VDD, an output of the twelfth D flip-flop U12 is configured to output the high Bian Siou signal DTH, an input of the nineteenth inverter U19 is configured to receive the low side dead zone comparison signal H5, an output of the nineteenth inverter U19 is connected to a CP input of the twelfth D flip-flop U22, an input of the twelfth D flip-flop U22 is configured to receive the clock input signal CLKin, and an input of the twelfth D flip-flop U22 is configured to output the low side dead zone signal DTH.
  9. 9. The automatic dead zone control circuit according to claim 1, wherein the logic combination module (52) comprises a seventh or gate U7 and a fifteenth or gate U15, wherein a first input terminal of the seventh or gate U7 is configured to receive a high-side dead zone control signal H1, a second input terminal of the seventh or gate U7 is configured to receive a high-side dead zone signal DTH, an output terminal of the seventh or gate U7 is configured to output a high-side drive signal H2, a first input terminal of the fifteenth or gate U15 is configured to receive a low-side dead zone control signal L1, a second input terminal of the fifteenth or gate U15 is configured to receive a low-side dead zone signal DTL, and an output terminal of the fifteenth or gate U15 is configured to output a low-side drive signal L2.
  10. 10. An LLC resonant converter comprising an automatic dead band control circuit according to any of claims 1-9.

Description

Automatic dead zone control circuit and LLC resonant converter Technical Field The application relates to the technical field of circuit control, in particular to an automatic dead zone control circuit and an LLC resonant converter. Background In the technical field of current power supplies, LLC resonant converters are widely applied to a plurality of high-efficiency power supply occasions by virtue of the advantages of high efficiency, energy conservation and the like. With the continuous improvement of the power performance requirements of electronic equipment, the performance optimization of the LLC resonant converter becomes an important direction of research. The development of the power supply technology not only promotes the progress of the power supply technology, but also provides powerful guarantee for the stable operation of various electronic equipment, and plays an important role in a plurality of fields such as industry, communication, consumer electronics and the like. In terms of dead zone control of an LLC resonant converter, the related art mainly has the following several schemes. The first is to use a mode of fixing the internal dead zone, i.e. preset dead zone time, and keep unchanged in the whole working process. This is relatively simple to implement and requires no additional adjustment means. The second is to set an adjustable dead zone through an external pin, so that a user can adjust the dead zone time through the external pin according to specific requirements, and the device has certain flexibility. The third is to realize automatic dead zone control by means of high-voltage capacitor, and dynamically adjust dead zone time by utilizing the characteristic of the high-voltage capacitor. However, these schemes of the related art have certain drawbacks. The scheme of fixed dead zone in inside can't carry out nimble adjustment according to actual working condition, is difficult to adapt to the work demand of different power tubes, has restricted half-bridge LLC resonant converter's performance. The external pins are provided with adjustable dead zones, and although the external pins have certain flexibility, additional pins and adjustment operations are needed, so that the complexity and the cost of the system are increased. And the automatic dead zone control is realized through the high-voltage capacitor, so that the additional high-voltage capacitor is needed, the cost is increased, and the problems of volume increase and the like can be caused. Disclosure of Invention In order to at least partially solve the above technical problems in the related art, the present application provides an automatic dead zone control circuit and an LLC resonant converter. In one aspect, the application provides an automatic dead zone control circuit, which adopts the following technical scheme: an automatic dead zone control circuit comprising: a maximum dead zone control circuit for generating a high side dead zone control signal H1 and a low side dead zone control signal L1 based on the clock input signal CLKin; A narrow pulse generating circuit, provided after the maximum dead zone control circuit, for generating a rising-edge narrow pulse signal Hon1 and a falling-edge narrow pulse signal Hoff1 based on the high-side driving signal H2; The level shift high-voltage tube driving and dead zone detection input circuit is connected with the narrow pulse generating circuit and is used for generating a high-side high-voltage tube opening signal Hon and a dead zone detection signal H3 based on the rising edge narrow pulse signal Hon1 and generating a high-side high-voltage tube closing signal Hoff based on the falling edge narrow pulse signal Hoff 1; The level shift and comparison circuit is connected with the level shift high-voltage tube driving and dead zone detection input circuit and is used for generating a high-side dead zone comparison signal H4 and a low-side dead zone comparison signal H5 based on the dead zone detection signal H3; The dead zone control logic circuit comprises a dead zone signal generation module and a logic combination module, wherein the dead zone signal generation module is connected with the level shift and comparison circuit and is used for generating a high-side dead zone signal DTH based on the high-side dead zone comparison signal H4 and a low-side dead zone signal DTL based on the low-side dead zone comparison signal H5, and the logic combination module is arranged between the maximum dead zone control circuit and the narrow pulse generation circuit and is connected with the dead zone signal generation module and is used for generating a high-side driving signal H2 based on the high-side dead zone control signal H1 and the high Bian Siou signal DTH and generating a low-side driving signal L2 based on the low-side dead zone control signal L1 and the low-side dead zone signal DTL. By adopting the technical scheme, the automatic dead zone control circuit can dynamical