CN-122001306-A - Apparatus and method for nonlinear cancellation of electronic systems

Abstract

The invention discloses an apparatus and a method for nonlinear cancellation in an electronic system. In some embodiments, the electronic system includes two or more circuit paths that process a common input signal in parallel, each circuit path including at least one instance of a circuit that behaves non-linearly. Thus, the nonlinear circuit is duplicated and contained at least once in each circuit path. Each circuit channel has an input scaling factor and an output scaling factor that can be changed from one circuit channel to another. The scaled output signals of the circuit channels are combined to generate a combined output signal. The input and output scaling factors are selected to eliminate or reduce non-linearities.

Inventors

• C. E. Alvarez Fonterra
• P. Delos

Assignees

• 亚德诺半导体国际无限责任公司

Dates

Publication Date

20260508

Application Date

20251028

Priority Date

20241106

Claims (20)

1. 1. An electronic system, comprising: two or more circuit channels configured to process an input signal in parallel to generate two or more output signals, wherein the two or more circuit channels comprise: A first circuit path including a first circuit block configured to receive an input signal scaled by a first input scaling factor, the first circuit path configured to generate a first output signal based on scaling an output of the first circuit block by a first output scaling factor, and A second circuit path including a second circuit block configured to receive an input signal scaled by a second input scaling factor, the second circuit path configured to generate a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have non-linearities, and An output combiner configured to combine two or more output signals including the first output signal and the second output signal to produce a combined output signal with non-linearities eliminated.
2. 2. The electronic system of claim 1, wherein the two or more circuit channels further comprise: A third circuit path including a third circuit block configured to receive the input signal scaled by a third input scaling factor, the third circuit path configured to generate a third output signal of the two or more output signals based on scaling an output of the third circuit block by a third output scaling factor.
3. 3. The electronic system of claim 1, wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.
4. 4. The electronic system of claim 3, wherein the input signal is an analog or radio frequency signal and the output signal is a digital signal.
5. 5. The electronic system of claim 1, wherein a plurality of input scaling factors including the first input scaling factor and the second input scaling factor define a matrix, and wherein a plurality of output scaling factors including the first output scaling factor and the second output scaling factor are based on an inverse of the matrix.
6. 6. The electronic system of claim 1, wherein the nonlinearity is a harmonic distortion component.
7. 7. The electronic system of claim 1, further comprising a calibration circuit configured to calibrate the first output scaling factor based on the detected value of the first input scaling factor and to calibrate the second output scaling factor based on the detected value of the second input scaling factor.
8. 8. The electronic system of claim 1, wherein the second circuit path further comprises one or more additional circuit blocks in parallel with the second circuit block, each of the one or more additional circuit blocks receiving an input signal scaled by the second input scaling factor.
9. 9. The electronic system of claim 8, wherein the second circuit path is further configured to generate the second output signal based on combining an output of each of the one or more additional circuit blocks with an output of the second circuit block.
10. 10. The electronic system of claim 1, wherein the second circuit block is a replica of the first circuit block.
11. 11. The electronic system of claim 1 implemented in a phased array antenna.
12. 12. A method of nonlinear cancellation, the method comprising: processing the input signal in parallel using two or more circuit channels to generate two or more output signals, wherein processing the input signal comprises: scaling the input signal by a first input scaling factor to generate a first scaled input signal for a first circuit block of a first circuit path; Generating a first output signal based on scaling an output of the first circuit block by a first output scaling factor; scaling the input signal with a second input scaling factor to generate a second scaled input signal for a second circuit block of a second circuit path; generating a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have non-linearities, and Two or more output signals including the first output signal and the second output signal are combined using an output combiner to generate a combined output signal in which non-linearities are eliminated.
13. 13. The method of claim 12, further comprising: Scaling the input signal by a third input scaling factor to generate a third scaled input signal for a third circuit block of a third circuit path, and A third output signal of the two or more output signals is generated based on scaling the output of the third circuit block by a third output scaling factor.
14. 14. The method of claim 12, wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.
15. 15. The method of claim 14, wherein the input signal is an analog or radio frequency signal and the output signal is a digital signal.
16. 16. The method of claim 12, wherein a plurality of input scaling factors including the first input scaling factor and the second input scaling factor define a matrix, and wherein a plurality of output scaling factors including the first output scaling factor and the second output scaling factor are based on an inverse of the matrix.
17. 17. The method of claim 12, wherein the nonlinearity is a harmonic distortion component.
18. 18. The method of claim 12, further comprising calibrating the first output scaling factor based on the detected value of the first input scaling factor and calibrating the second output scaling factor based on the detected value of the second input scaling factor.
19. 19. The method of claim 12, wherein the second circuit path further comprises one or more additional circuit blocks in parallel with the second circuit block, the method further comprising providing an input signal scaled by the second input scaling factor to each of the one or more additional circuit blocks, and generating the second output signal based on combining an output of each of the one or more additional circuit blocks with an output of a second circuit block.
20. 20. The method of claim 12, wherein the second circuit block is a replica of the first circuit block.

Description

Apparatus and method for nonlinear cancellation of electronic systems Technical Field The disclosed technology relates generally to electronics, and more particularly to nonlinear cancellation of circuit blocks. Background Some circuits require linear operation such that the output signal varies in a linear relationship with respect to the applied input signal. However, various non-idealities may cause the output signal to exhibit a non-linear relationship with respect to the applied input signal. Such non-linear behavior may come from a variety of sources including, but not limited to, component mismatch, process variations, supply voltage constraints, temperature variations, signal amplitude saturation, and/or various other sources. Disclosure of Invention The invention discloses an apparatus and a method for nonlinear cancellation in an electronic system. In some embodiments, the electronic system includes two or more circuit paths that process a common input signal in parallel, each circuit path including at least one instance of a circuit that behaves non-linearly. Thus, the nonlinear circuit is duplicated and contained at least once in each circuit path. Each circuit channel has an input scaling factor and an output scaling factor that can be changed from one circuit channel to another. The scaled output signals of the circuit channels are combined to generate a combined output signal. The input and output scaling factors are selected to eliminate or reduce non-linearities. Thus, by selecting appropriate values of the input and output scaling factors, non-linear cancellation may be achieved. For example, the teachings herein may be used to eliminate or reduce various nonlinearities, including but not limited to third order harmonic distortion. The nonlinear cancellation schemes herein may have relatively lower complexity and/or higher speed than calibration schemes that suffer from additive sequences and/or convergence delays. The nonlinear cancellation technique can be applied to a wide variety of electronic systems including, for example, data conversion systems and phased array antenna systems. In one aspect, an electronic system includes two or more circuit channels configured to process input signals in parallel to generate two or more output signals. The two or more circuit channels include a first circuit channel including a first circuit block configured to receive an input signal scaled by a first input scaling factor, the first circuit channel configured to generate a first output signal based on scaling an output of the first circuit block by a first output scaling factor. The two or more circuit channels further include a second circuit channel including a second circuit block configured to receive an input signal scaled by a second input scaling factor, the second circuit channel configured to generate a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have nonlinearities. The electronic system further includes an output combiner configured to combine two or more output signals including the first output signal and the second output signal to produce a combined output signal with non-linearities eliminated. In another aspect, a method of nonlinear cancellation includes processing an input signal in parallel using two or more circuit channels to generate two or more output signals. Processing the input signal includes scaling the input signal by a first input scaling factor to generate a first scaled input signal for a first circuit block of a first circuit channel, generating a first output signal based on scaling an output of the first circuit block by a first output scaling factor, scaling the input signal by a second input scaling factor to generate a second scaled input signal for a second circuit block of a second circuit channel, and generating a second output signal based on scaling an output of the second circuit block by a second output scaling factor. The first circuit block and the second circuit block have nonlinearities, and the method further comprises combining, using an output combiner, two or more output signals including the first output signal and the second output signal to generate a combined output signal in which nonlinearities are eliminated. Drawings FIG. 1A is a schematic diagram of an electronic system according to one embodiment. Fig. 1B is a schematic diagram of an electronic system according to another embodiment. FIG. 2 is a schematic diagram of a data conversion system according to one embodiment. Fig. 3A is a schematic diagram of a data conversion system according to another embodiment. Fig. 3B is a schematic diagram of a data conversion system according to another embodiment. Fig. 4 is a schematic diagram of an electronic system according to another embodiment. Fig. 5A is a schematic diagram of one embodiment of a phased array antenna