CN-122001337-A - 21 Pipe D trigger circuit of low electric leakage

Abstract

The invention provides a low-leakage 21-tube D trigger circuit which consists of 10 PMOS tubes P0-P9 and 11 NMOS tubes N0-N10, wherein a main locking end is formed, P1 and P3 drains are connected with N0 drains, P4 and N3 grids to form a shared node i, N0 sources are connected to N10 and N1 parallel nodes, N0 grids are shared with N2 sources, P4 drains, N3 drains and N4 grids to form an internal node ii, N3 and N4 sources are respectively connected with N5 drains, N4 drains and P5 drains are connected to form a main locking structure output node iii, P5 gates are connected with N2 drains, slave latch ends, P6, P7 and N6 and N7 realize a cross coupling structure, N8 drains are connected with N7 sources, N8 gates are connected with P8 drains and are jointly connected to P5 gates and N2 drains, and an effective solution is provided for customizing a digital chip based on a standard cell library.

Inventors

• ZHANG XUMENG
• LI CHENYANG
• LIU QI
• LIU MING

Assignees

• 复旦大学

Dates

Publication Date

20260508

Application Date

20251111

Claims (2)

1. 1. A low-leakage 21-pipe D trigger circuit consists of 10 PMOS pipes P0-P9 and 11 NMOS pipes N0-N10, and is characterized in that a main stage part of the trigger consists of P0-P4 of the PMOS pipes, N0-N3 of the NMOS pipes and N10 of the NMOS pipes, and a secondary stage part of the trigger consists of P5-P9 of the PMOS pipes and N4-N9 of the NMOS pipes, wherein: The sources of P0, P4, P5, P6, P8 and P9 of the PMOS tube are all connected with a power supply, the sources of N1, N5, N6, N8, N9 and N10 of the NMOS tube are all connected with a ground terminal, a clock CLK is respectively connected with P0 and P8 of the PMOS tube and the gates of N1, N5 and N10 of the NMOS tube, an input signal D is respectively connected with the gate of P1 and the source of P2 of the PMOS tube, and the drain of P0 of the PMOS tube is respectively connected with the sources of P1 and P7 of the PMOS tube; At the main latch end, the drains of P1 and P3 of the PMOS tube are respectively connected with the drain of N0 of the NMOS tube, the P4 of the PMOS tube and the grid of N3 of the NMOS tube to form a shared node i, the source of N0 of the NMOS tube is connected to the parallel node of N10 and N1 of the NMOS tube, the grid of N0 of the NMOS tube is shared with the source of N2, the drain of P4, the drain of N3 and the grid of N4 to form an internal node ii, the sources of N3 and N4 of the NMOS tube are respectively connected with the drain of N5, the drain of N4 of the NMOS tube is connected with the drain of P5 of the PMOS tube to form an output node iii of the main latch structure, and the grid of P5 of the PMOS tube is connected with the drain of N2 of the NMOS tube; At the slave latch end, an output node iii of the main latch structure is respectively connected with the grid electrodes of P6 and P9 of the PMOS tube, the grid electrodes of N6 and N9 of the NMOS tube and the drain electrodes of P7 of the PMOS tube and N7 of the NMOS tube, the drain electrodes of P6 of the PMOS tube and N6 of the NMOS tube are connected with the grid electrodes of P7 of the PMOS tube and N7 of the NMOS tube, so that the P6 and P7 of the PMOS tube and the N6 and N7 of the NMOS tube realize a cross coupling structure, the drain electrode of N8 of the NMOS tube is connected with the source electrode of N7 of the NMOS tube, the grid electrode of N8 of the NMOS tube is connected with the drain electrode of P8 of the PMOS tube, and the grid electrode of P5 of the PMOS tube and the drain electrode of N2 of the NMOS tube are commonly connected; The clock CLK controls the P0 and P2 of the PMOS tube to determine whether the input signal D is transmitted to the latch end inside the main pole, when the clock CLK is at a high level, the input signal D is isolated outside, when the clock CLK is at a low level, the P0 and P1 of the PMOS tube are simultaneously started to pull up the drain electrode of the N0 of the NMOS tube to a high level, when the clock CLK is at a low level, the P2 of the turned-on PMOS tube transmits the high level to the gate electrode of the N0, so that the N0 and N1 of the turned-on NMOS tube pull down the drain electrode of the N0 of the NMOS tube to a low level together, and when the clock CLK is at a low level, the input signal D does not generate any path to ground when passing through the P2 of the PMOS tube, thereby inhibiting the generation of a dynamic node; When the clock CLK is high, the slave stage transmits low level to the P6 of the NMOS tube and the N6 of the NMOS tube if the master stage latch part drives the N4 gate of the NMOS tube to high level, and the N4 of the NMOS tube is in a closed state if the master stage latch part drives the N4 gate of the NMOS tube to low level, and meanwhile, the grid voltage of the N4 of the NMOS tube is transmitted to the P5 gate of the PMOS tube through the N2 of the NMOS tube which is conducted, so that the pull-up path of the P6 of the PMOS tube and the N2 of the N6 gate of the NMOS tube is activated, and the N4 of the NMOS tube is controlled by the clock CLK between the N4 of the NMOS tube and the P5 gate of the PMOS tube, so as to compensate the defect that the N4 of the NMOS tube cannot simultaneously transmit high level and low level.
2. 2. A control method of a low leakage 21-pipe D flip-flop circuit according to claim 1, wherein the operation state of the flip-flop under different input configurations is as follows, (1) When the input signal D is low level and the clock CLK is low level, P0 and P8 of the PMOS tube are in a conducting state, P6 and P7 of the PMOS tube and sources of N6 and N7 of the NMOS tube are connected with a power supply end VDD or VSS, N2 and N5 of the NMOS tube are in a closing state, any change of the grid voltage of N4 of the NMOS tube does not affect the internal node of the slave latch structure, the state of the output node Q is kept, the P1 of the PMOS tube inputs high level to the P4 of the PMOS tube and the grid of N3 of the NMOS tube at the same time, and all nodes in the main stage are not in competition due to the fact that N5 of the NMOS tube is in the closing state; (2) When the input signal D is low level and the clock CLK is high level, the drain electrode data of N4 and P5 of the NMOS tube are transmitted to an output node Q from the stage part, wherein the state of the output node Q is determined by a feedback loop formed by P3 of the PMOS tube and N2, N3 and N5 of the NMOS tube in the main latch, and the logic high level stored in the N3 grid of the NMOS tube is conducted with the N5 of the NMOS tube, so that the N2 of the NMOS tube transmits the logic low level to the grid of P3 of the PMOS tube, and the logic high level of the N3 grid of the NMOS tube is further enhanced; (3) When the input signal D is at a high level and the clock CLK is at a low level, as described in (1), the latch structure of the slave stage part can keep the state of the output node Q, but the input signal D can close the P1 of the PMOS tube, open the N1 of the NMOS tube and pull down the source of the N0 of the NMOS tube; (4) When the input signal D is at a high level and the clock CLK is at a high level, contrary to the situation of (2), the P4 of the PMOS tube and the N0 and N1 of the NMOS tube in the main stage form a latch path, the grid electrode of the N0 of the NMOS tube is clamped to a logic high level, the grid electrode of the P4 of the PMOS tube is clamped to a logic low level, and finally the logic high level is ensured to be transmitted to the output node Q.

Description

21 Pipe D trigger circuit of low electric leakage Technical Field The invention relates to a low-leakage 21-tube D trigger circuit which can realize a reliable data capturing and latching function in a near-threshold voltage range. In order to reduce the layout area and static power consumption of the trigger unit, the structure performs device multiplexing and topology structure modification on a traditional 24-tube trigger (Transmission-Gate Flip-Flop) circuit provided by a standard unit library, and realizes that the trigger circuit with single-phase clock control is built by using only 21 transistors. Background Today, where semiconductor processes approach physical limits, the PPA (power consumption, performance, area) of custom digital chips is increasingly dependent on the optimization of the "standard cell library" which is the lowest level cell. Under the same action level description statement, a set of deeply customized unit libraries is replaced, and the great main frequency improvement and power consumption improvement can be realized under the same area. The flip-flop, which is a component of the standard cell library, no longer has a simple data registering function, and is a common bottleneck for three battlefields of timing closure, power consumption budget and area compression. Under advanced nodes, the flip-flop is both the maximum load of the clock and the primary victim of glitches and clock skew. A flip-flop with non-optimized leakage power consumption may occupy up to 50% of the static power consumption in the chip. At the same Time, the AI accelerator, multiple timing paths within the CPU micro-architecture all meet at the trigger port, and any insufficient Setup/Hold Time (Setup/Hold Time) margin can result in a reduced chip dominant frequency or force the insertion of additional buffers to increase chip area. In summary, the competing focus of modern standard cell libraries has converged to flip-flops, how to optimize flip-flops with fewer transistors, lower leakage, and better timing performance has become the primary technological route for flip-flop optimization. Many methods for optimizing flip-flops are currently proposed, including single-phase clock load control, redundant clock path optimization, the introduction of additional functional blocks, etc. But in implementation at the expense of area or the ability to operate at low voltages. This also makes optimizing the power consumption and area of the flip-flop from the bottom layer a major challenge. Disclosure of Invention The invention aims to provide a 21-tube D trigger circuit with low electric leakage. The invention changes the internal data latch path by modifying the topology structure based on the traditional trigger TGFF, the structure can realize stable and reliable data register function in a wider voltage range, in addition, the internal time sequence of the trigger is also regulated to be single-phase clock control, the number of transistors required by the whole structure is reduced, and further, the layout area is reduced and the static power consumption of the circuit is reduced. The invention provides a low-leakage 21-pipe D trigger circuit, which consists of 10 PMOS pipes P0-P9 and 11 NMOS pipes N0-N10, wherein a main stage part of the trigger consists of PMOS pipes P0-P4, NMOS pipes N0-N3 and NMOS pipes N10, and a secondary stage part of the trigger consists of PMOS pipes P5-P9 and NMOS pipes N4-N9, wherein the main stage part of the trigger consists of the following components of the main stage part of the trigger: The sources of P0, P4, P5, P6, P8 and P9 of the PMOS tube are all connected with a power supply, the sources of N1, N5, N6, N8, N9 and N10 of the NMOS tube are all connected with a ground terminal, a clock CLK is respectively connected with P0 and P8 of the PMOS tube and the gates of N1, N5 and N10 of the NMOS tube, an input signal D is respectively connected with the gate of P1 and the source of P2 of the PMOS tube, and the drain of P0 of the PMOS tube is respectively connected with the sources of P1 and P7 of the PMOS tube; At the main latch end, the drains of P1 and P3 of the PMOS tube are respectively connected with the drain of N0 of the NMOS tube, the P4 of the PMOS tube and the grid of N3 of the NMOS tube to form a shared node i, the source of N0 of the NMOS tube is connected to the parallel node of N10 and N1 of the NMOS tube, the grid of N0 of the NMOS tube is shared with the source of N2, the drain of P4, the drain of N3 and the grid of N4 to form an internal node ii, the sources of N3 and N4 of the NMOS tube are respectively connected with the drain of N5, the drain of N4 of the NMOS tube is connected with the drain of P5 of the PMOS tube to form an output node iii of the main latch structure, and the grid of P5 of the PMOS tube is connected with the drain of N2 of the NMOS tube; At the slave latch end, an output node iii of the main latch structure is respectively connected with th