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CN-122001343-A - Comparator rapid calibration circuit and method applied to duty cycle monitoring circuit

CN122001343ACN 122001343 ACN122001343 ACN 122001343ACN-122001343-A

Abstract

The invention provides a comparator rapid calibration circuit and a comparator rapid calibration method applied to a duty ratio monitoring circuit, wherein the circuit comprises a low-pass filtering module, a selecting module and a comparing module; the output end of the low-pass filtering module is connected with the input end of the selecting module, the output end of the selecting module is connected with the input end of the comparing module, an input clock signal enters the selecting module through the low-pass filtering module, the selecting module selects signals from the reference signals and the input clock signal to be input into the positive input end of the comparing module, the reference signals are also input into the negative input end of the comparing module, the selecting module defaults to select the reference signals to be connected into the positive input end of the comparator, the circuit enters a comparator offset voltage calibration mode, and an offset voltage error between the positive input end and the negative input end is output by the comparator. Calibration of offset_N [5:0] and offset_P [5:0] requires 6 comparisons according to the present invention, whereas conventional schemes require 128 comparisons for scanning one by one, greatly improving calibration speed.

Inventors

  • MAO LICHEN
  • ZHANG XIAOLUO
  • Cheng Qingkai
  • WANG HONGPENG

Assignees

  • 南京博茵微电子有限公司

Dates

Publication Date
20260508
Application Date
20260123

Claims (10)

  1. 1. The comparator rapid calibration circuit applied to the duty ratio monitoring circuit is characterized by comprising a low-pass filtering module, a selecting module and a comparing module; The output end of the low-pass filtering module is connected with the input end of the selecting module and is used for filtering input signals; The output end of the selection module is connected with the input end of the comparison module; The input clock signal enters the selection module through the low-pass filtering module, the selection module selects signals from the reference signals and the input clock signal to be input into the positive input end of the comparison module, the reference signals are also input into the negative input end of the comparison module, the selection module defaults to select the reference signals to be connected into the positive input end of the comparator, the circuit enters the offset voltage calibration mode of the comparator, and the comparator outputs offset voltage errors between the positive input end and the negative input end.
  2. 2. The comparator rapid calibration circuit for a duty cycle monitoring circuit of claim 1 further comprising a first selector, a second selector, and a first flip-flop; the clock signal output by the duty ratio adjusting module is respectively and directly input to the positive input end and the negative input end of the first selector through the delay line; The output end of the first selector is connected with the positive input end of the second selector, and the output end of the first selector is connected with the low-pass filtering module; The output of the low-pass filtering module is connected with the input end of the selecting module; the negative input end of the comparison module is connected with a reference signal, and the output end of the comparison module is connected with the D end of the first trigger; The Q end of the first trigger is connected with the control logic module.
  3. 3. A comparator rapid calibration circuit for use in a duty cycle monitoring circuit according to claim 2, wherein the selection module comprises a first transmission gate and a second transmission gate; The output end of the first transmission gate is connected with the output end of the second transmission gate to be used as the input of the positive input end of the comparison module; The input end of the second transmission gate is connected with a reference signal.
  4. 4. A comparator rapid calibration circuit for a duty cycle monitoring circuit according to claim 3 further comprising a logic control module; The logic control module is respectively connected with the first selector, the second selector, the comparison module, the selection module and the first trigger; The logic control module controls the first selector through a signal clk_sel1 and controls the second selector through a signal clk_sel0; the logic control module controls the selection module through a signal dcm_offset_en; the logic control module controls the comparison module through the signal dcm_en and the signal offset_N [5:0], and the signal offset_P [5:0 ].
  5. 5. A comparator rapid calibration method applied to a duty cycle monitoring circuit, applied to a comparator rapid calibration circuit applied to a duty cycle monitoring circuit as claimed in any one of claims 1 to 4, comprising: Setting a calibration signal of the comparison module; Obtaining an output signal of a comparison module; and adjusting the calibration signal of the comparison module according to the output signal of the comparison module to calibrate the comparison module.
  6. 6. A method of fast calibration of a comparator for use in a duty cycle monitoring circuit as recited in claim 5, wherein setting the calibration signal of the comparison module comprises: the output signals of the logic control module, offset_P [5:0] and offset_N [5:0], are set to 6' b00000 to be input into the comparison module.
  7. 7. A method for quickly calibrating a comparator applied to a duty cycle monitoring circuit according to claim 5, wherein adjusting the calibration signal of the comparison module according to the output signal of the comparison module comprises: Acquiring an output signal dcm_out of a first trigger; The output signal dcm_out of the first trigger is 0, the voltage of the P terminal is smaller than the voltage of the N terminal, and the offset_P is regulated; Setting offset_p [5:0] =6 'b100000, step=6' b010000, flag=0, waiting for the output signal dcm_out of the first flip-flop to be valid; if the output signal dcm_out=1, offset_p [5:0] =offset_p [5:0] -step, step=step/2, flag=flag+1; if the output signal dcm_out=0, offset_p [5:0] =offset_p [5:0] +step, step=step/2, flag=flag+1; If flag=5, the comparison module calibration is ended.
  8. 8. A method for quickly calibrating a comparator applied to a duty cycle monitoring circuit according to claim 5, wherein adjusting the calibration signal of the comparison module according to the output signal of the comparison module comprises: Acquiring an output signal dcm_out of a first trigger; the output signal dcm_out of the first trigger is 1, the voltage of the P terminal is larger than that of the N terminal, and the offset_N is regulated; Setting offset_n [5:0] =6 'b100000, step=6' b010000, flag=0, waiting for the output signal dcm_out of the first flip-flop to be valid; if the output signal dcm_out=0, offset_n [5:0] =offset_n [5:0] -step, step=step/2, flag=flag+1; if the output signal dcm_out=1, offset_n [5:0] =offset_n [5:0] +step, step=step/2, flag=flag+1; If flag=5, the comparison module calibration is ended.
  9. 9. An electronic device comprising a chip, a processor and a memory, the memory storing computer program code comprising computer instructions, the electronic device performing a comparator fast calibration method for a duty cycle monitoring circuit as claimed in any one of claims 5 to 8 when the chip executes the computer instructions.
  10. 10. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, the computer program comprising program instructions which, when executed by a processor of an electronic device, cause the processor to perform a comparator fast calibration method applied to a duty cycle monitoring circuit according to any one of claims 5 to 8.

Description

Comparator rapid calibration circuit and method applied to duty cycle monitoring circuit Technical Field The invention relates to the technical field of integrated circuits, in particular to a comparator rapid calibration circuit and a comparator rapid calibration method applied to a duty ratio monitoring circuit. Background In the field of memory technology, DCM (duty cycle monitor) is widely used in DDR (Double DATA RATE SDRAM, double data rate synchronous dynamic random access memory) and HBM (High Bandwidth Memory ) technologies nowadays, and in the memory technology, the requirements on stability and reliability of signals are more strict by the improvement of data transmission rate. The DCM module can monitor the clock signal (data needs to be clock sampled) in real time, ensuring the integrity and accuracy of the data during high frequency transmission. For example, in DDR5, the data rate may reach 3200-6400MT/s, and at such high data rate, any duty cycle abnormality may cause data transmission errors, so that the DCM can timely detect and feed back the abnormalities, so that the DCA (Duty Cycle Adjust) module performs corresponding adjustment and optimization, which improves the memory performance and provides a powerful guarantee for stable operation of the whole system. In the memory technology field, DCM is typically bound to DCA modules. The existing DCM and DCA circuits generally adopt the combination of analog detection and digital calibration, wherein the DCM module carries out duty cycle detection by an analog circuit, filters a clock signal by a low-pass filter, retains a direct current component (which can reflect the duty cycle), compares the direct current component with a reference voltage by a comparator, finally outputs the relation between the current duty cycle and the ideal duty cycle, and a digital control circuit generates a control signal to the DCA module according to the output result so as to realize the accurate adjustment of the duty cycle of the clock signal. In addition, temperature variation, noise interference and the like can also influence the performance of the transistor, so that parameters of the transistor are changed, further the threshold voltage of the comparator is influenced, and errors are generated, therefore, the comparator needs to be calibrated before duty cycle detection so as to ensure the accuracy of duty cycle feedback. Because of the reasons of manufacturing process and the like, the error of the comparator is unavoidable, more mos tubes are introduced to make up the error of the comparator as much as possible, the adjusting ranges of the offset_p and the offset_n become large, the time is long by using the progressive scanning method, and the existing scheme cannot solve the problem. The existing Duty Cycle Monitor scheme only detects the clock output from DELAY LINE after the DCA module is regulated, cannot intuitively see the regulating capability of the DCA module, and cannot evaluate the influence of DELAY LINE on the duty ratio. The existing Duty Cycle Monitor scheme uses a single CMOS transmission gate to control the connection between the P-terminal and the N-terminal, which is too simple and may interfere with the normal calibration process if the operation is improper or signal interference occurs. Disclosure of Invention The invention aims to provide a comparator rapid calibration circuit and a method applied to a duty ratio monitoring circuit, wherein the method replaces a linear calibration scheme of offset voltage by a dichotomy, and the calibration of offset_N [5:0] and offset_P [5:0] is required to be compared for 6 times according to the invention, while the traditional scheme is required to be compared for 128 times one by one in a scanning way, so that the calibration speed is greatly improved. A comparator rapid calibration circuit applied to a duty ratio monitoring circuit comprises a low-pass filtering module, a selecting module and a comparing module; the output end of the low-pass filtering module is connected with the input end of the selecting module and is used for filtering the input clock signal; The output end of the selection module is connected with the input end of the comparison module; The input clock signal enters the selection module through the low-pass filter module, the selection module selects signals from the reference signals and the input clock signal to be input into the positive input end of the comparison module, the selection module defaults to select the reference signals to be connected into the positive input end of the comparator, the circuit enters a comparator offset voltage calibration mode, and the comparator outputs offset voltage errors between the positive input end and the negative input end. Preferably, the device further comprises a first selector, a second selector and a first trigger; the signal output by the duty ratio adjusting module is respectively and directly input to the positive