CN-122001344-A - Comparator circuit for performing comparator offset calibration and method of operating the same

Abstract

A comparison circuit and method of operating a comparison circuit are provided that perform comparator offset calibration. The comparison circuit includes a comparator and a multiplexer. The comparator includes at least one transistor and generates a first output signal based on the first input signal, the second input signal, and the operating clock signal. The multiplexer outputs a first clock signal as an operation clock signal based on the control signal in the normal mode, and outputs a second clock signal different from the first clock signal as the operation clock signal based on the control signal in the offset calibration mode. In the offset calibration mode, the comparison circuit is configured to perform an offset calibration operation by degrading at least one transistor based on the first and second input signals having the same voltage level and the operation clock signal.

Inventors

• Yu Jiongzhen
• Yin Junxie
• QUAN WUXING

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20251106

Priority Date

20241108

Claims (20)

1. 1. A comparison circuit, comprising: a comparator including at least one transistor and configured to generate a first output signal based on the first input signal, the second input signal, and the operation clock signal, and A multiplexer configured to: in the normal mode, a first clock signal is output as the operation clock signal based on the control signal, and In an offset calibration mode, a second clock signal different from the first clock signal is output as the operation clock signal based on the control signal, Wherein, in the offset calibration mode, the comparison circuit is configured to perform an offset calibration operation by degrading the at least one transistor based on the first and second input signals having the same voltage level and the operation clock signal.
2. 2. The comparison circuit of claim 1, wherein the comparator comprises: A first p-channel metal oxide semiconductor PMOS transistor and a second PMOS transistor connected in parallel between a terminal to which a power supply voltage is applied and a terminal from which the first output signal is output, the first PMOS transistor including a gate terminal connected to a terminal to which the operation clock signal is input, the second PMOS transistor including a gate terminal connected to a terminal from which the second output signal is output; A third PMOS transistor and a fourth PMOS transistor connected in parallel between a terminal to which the power supply voltage is applied and a terminal from which the second output signal is output, the third PMOS transistor including a gate terminal connected to a terminal from which the first output signal is output, the fourth PMOS transistor including a gate terminal connected to a terminal to which the operation clock signal is input; A first n-channel metal oxide semiconductor NMOS transistor and a second NMOS transistor connected in series between a terminal from which the second output signal is output and a first node, the first NMOS transistor including a gate terminal connected to the terminal from which the first output signal is output, the second NMOS transistor including a gate terminal connected to the terminal to which the first input signal is input; A third NMOS transistor and a fourth NMOS transistor connected in series between the terminal from which the first output signal is output and the first node, the third NMOS transistor including a gate terminal connected to the terminal from which the second output signal is output, the fourth NMOS transistor including a gate terminal connected to the terminal to which the second input signal is input, and A fifth NMOS transistor that is connected between the first node and a ground node, and that includes a gate terminal connected to a terminal to which the operation clock signal is input.
3. 3. The comparison circuit of claim 2, wherein, in the normal mode, each gate terminal of the first PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor is configured to receive the first clock signal having a first frequency.
4. 4. The comparison circuit of claim 3, wherein, in the offset calibration mode, each gate terminal of the first PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor is configured to receive the second clock signal having a second frequency that is lower than the first frequency.
5. 5. The comparison circuit of claim 4, wherein in the offset calibration mode, one of the second PMOS transistor and the third PMOS transistor is configured to repeatedly turn on and off, and the other of the second PMOS transistor and the third PMOS transistor is configured to turn off.
6. 6. The comparison circuit of claim 4, wherein in the offset calibration mode: When the voltage level of the gate terminal of the second NMOS transistor is higher than the voltage level of the gate terminal of the fourth NMOS transistor, the third PMOS transistor is configured to be turned off, and the second PMOS transistor is configured to be repeatedly turned on and off, and When the voltage level of the gate terminal of the fourth NMOS transistor is higher than the voltage level of the gate terminal of the second NMOS transistor, the third PMOS transistor is configured to be repeatedly turned on and off, and the second PMOS transistor is configured to be turned off.
7. 7. The comparison circuit of claim 6 wherein, in the offset calibration mode, when the voltage level of the gate terminal of the second NMOS transistor is higher than the voltage level of the gate terminal of the fourth NMOS transistor, the second PMOS transistor is configured to have degraded performance outside of a reference performance range, and the third PMOS transistor is configured to have maintained performance within the reference performance range.
8. 8. The comparison circuit as claimed in claim 7, wherein in the offset calibration mode, when the voltage level of the gate terminal of the second NMOS transistor is higher than the voltage level of the gate terminal of the fourth NMOS transistor, the voltage level of the threshold voltage of the second PMOS transistor is lowered.
9. 9. The comparison circuit of claim 6 wherein, in the offset calibration mode, when the voltage level of the gate terminal of the fourth NMOS transistor is higher than the voltage level of the gate terminal of the second NMOS transistor, the third PMOS transistor is configured to have degraded performance outside of a reference performance range, and the second PMOS transistor is configured to have maintained performance within the reference performance range.
10. 10. The comparison circuit of claim 1, wherein the comparator comprises: A fifth PMOS transistor which is connected between a terminal to which a power supply voltage is applied and the second node, and which includes a gate terminal connected to a terminal to which an inverted operation clock signal is input, wherein the inverted operation clock signal is an inverted signal of the operation clock signal; A sixth PMOS transistor and a sixth NMOS transistor connected in series between the second node and the ground node, the sixth PMOS transistor including a drain terminal connected to the terminal from which the first output signal is output and a gate terminal connected to the terminal from which the second output signal is output, the sixth NMOS transistor including a drain terminal connected to the terminal from which the first output signal is output and a gate terminal connected to the terminal from which the second output signal is output; A seventh PMOS transistor and a seventh NMOS transistor connected in series between the second node and the ground node, the seventh PMOS transistor including a drain terminal connected to the terminal from which the second output signal is output and a gate terminal connected to the terminal from which the first output signal is output, the seventh NMOS transistor including a drain terminal connected to the terminal from which the second output signal is output and a gate terminal connected to the terminal from which the first output signal is output; An eighth PMOS transistor and an eighth NMOS transistor connected in series between the terminal to which the power supply voltage is applied and the third node, the eighth PMOS transistor including a gate terminal connected to the terminal to which the operation clock signal is input, and the eighth NMOS transistor including a gate terminal connected to the terminal to which the first input signal is input; A ninth PMOS transistor and a ninth NMOS transistor connected in series between the terminal to which the power supply voltage is applied and the third node, the ninth PMOS transistor including a gate terminal connected to the terminal to which the operation clock signal is input, the ninth NMOS transistor including a gate terminal connected to the terminal to which the second input signal is input; a tenth NMOS transistor that includes a drain terminal connected to the drain terminal of the sixth NMOS transistor and a gate terminal connected to the drain terminal of the eighth PMOS transistor; an eleventh NMOS transistor including a drain terminal connected to the drain terminal of the seventh NMOS transistor and a gate terminal connected to the drain terminal of the ninth PMOS transistor, and A twelfth NMOS transistor that is connected between the third node and the ground node, and that includes a gate terminal connected to a terminal to which the operation clock signal is input.
11. 11. The comparison circuit of claim 10, wherein in the offset calibration mode, one of the sixth PMOS transistor and the seventh PMOS transistor is configured to be repeatedly turned on and off, and the other of the sixth PMOS transistor and the seventh PMOS transistor is configured to be turned off.
12. 12. The comparison circuit as claimed in claim 11, wherein, in the offset calibration mode, when a voltage level of the gate terminal of the eighth NMOS transistor is higher than a voltage level of the gate terminal of the ninth NMOS transistor, a voltage level of the threshold voltage of the sixth PMOS transistor is lowered.
13. 13. The comparison circuit of claim 11, wherein in the offset calibration mode, when a voltage level of a gate terminal of the ninth NMOS transistor is higher than a voltage level of a gate terminal of the eighth NMOS transistor, the seventh PMOS transistor is configured to have degraded performance outside a reference performance range, and the sixth PMOS transistor is configured to have maintained performance within the reference performance range.
14. 14. The comparison circuit of claim 10, wherein in the offset calibration mode: When the voltage level of the gate terminal of the eighth NMOS transistor is higher than the voltage level of the gate terminal of the ninth NMOS transistor, the sixth PMOS transistor is configured to be repeatedly turned on and off, and the seventh PMOS transistor is configured to be turned off, and When the voltage level of the gate terminal of the ninth NMOS transistor is higher than the voltage level of the gate terminal of the eighth NMOS transistor, the sixth PMOS transistor is configured to be turned off, and the seventh PMOS transistor is configured to be repeatedly turned on and off.
15. 15. The comparison circuit of claim 1, wherein the comparison circuit is configured to: during the manufacturing process of the comparison circuit, performing the offset calibration operation in the offset calibration mode, and After the manufacturing process of the comparison circuit, a normal operation is performed in the normal mode.
16. 16. The comparison circuit of claim 1, further comprising: A switch connected between an input terminal to which the first input signal is input and an input terminal to which the second input signal is input, the switch being configured to be opened in the normal mode and closed in the offset calibration mode based on the control signal.
17. 17. A method of operating a comparison circuit comprising at least one transistor, the method comprising: determining whether an operation mode of the comparison circuit is an offset calibration mode or a normal mode; Performing an offset calibration operation by degrading the at least one transistor based on first and second input signals having the same voltage level and an operation clock signal when the operation mode of the comparison circuit is the offset calibration mode, and When the operation mode of the comparison circuit is the normal mode, normal operation is performed based on the first and second input signals having different voltage levels and the operation clock signal.
18. 18. The method of claim 17, wherein performing the normal operation comprises: outputting a first clock signal as the operation clock signal based on a control signal; Receiving said first input signal and said second input signal having different voltage levels, and A first output signal is generated based on the first input signal, the second input signal, and the first clock signal.
19. 19. The method of claim 17, wherein performing the offset calibration operation comprises: outputting a second clock signal as the operation clock signal based on a control signal; receiving the first input signal and the second input signal having the same voltage level, and A first output signal is generated based on the first input signal, the second input signal, and the second clock signal.
20. 20.A comparison circuit, comprising: a comparator including at least one transistor and configured to generate a first output signal based on the first input signal, the second input signal, and the operation clock signal, and A multiplexer configured to: In a normal mode, outputting a first clock signal as the operation clock signal based on a control signal; In an offset calibration mode, a second clock signal different from the first clock signal is output as the operation clock signal based on the control signal, Wherein, in the offset calibration mode, the first input signal and the second input signal have the same voltage level, Wherein the comparator comprises: A first p-channel metal oxide semiconductor PMOS transistor and a second PMOS transistor connected in parallel between a terminal to which a power supply voltage is applied and a terminal from which the first output signal is output, the first PMOS transistor including a gate terminal connected to a terminal to which the operation clock signal is input, the second PMOS transistor including a gate terminal connected to a terminal from which the second output signal is output; A third PMOS transistor and a fourth PMOS transistor connected in parallel between a terminal to which the power supply voltage is applied and a terminal from which the second output signal is output, the third PMOS transistor including a gate terminal connected to a terminal from which the first output signal is output, the fourth PMOS transistor including a gate terminal connected to a terminal to which the operation clock signal is input; A first n-channel metal oxide semiconductor NMOS transistor and a second NMOS transistor connected in series between a terminal from which the second output signal is output and a first node, the first NMOS transistor including a gate terminal connected to the terminal from which the first output signal is output, the second NMOS transistor including a gate terminal connected to the terminal to which the first input signal is input; A third NMOS transistor and a fourth NMOS transistor connected in series between the terminal from which the first output signal is output and the first node, the third NMOS transistor including a gate terminal connected to the terminal from which the second output signal is output, the fourth NMOS transistor including a gate terminal connected to the terminal to which the second input signal is input, and A fifth NMOS transistor connected between the first node and a ground node and including a gate terminal connected to a terminal to which the operation clock signal is input, Wherein, in the offset calibration mode, when the voltage level of the gate terminal of the second NMOS transistor is higher than the voltage level of the gate terminal of the fourth NMOS transistor, the comparison circuit is configured such that the second PMOS transistor has a reduced threshold voltage, and Wherein the comparison circuit is configured to: Performing an offset calibration operation in the offset calibration mode during a manufacturing process of the comparison circuit, an After the manufacturing process of the comparison circuit, a normal operation is performed in the normal mode.

Description

Comparator circuit for performing comparator offset calibration and method of operating the same Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2024-0157958 filed in the Korean Intellectual Property Office (KIPO) at 11/8 of 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Example embodiments relate generally to semiconductor integrated circuits and, more particularly, to a comparison circuit that performs comparator offset calibration and a method of operating the comparison circuit. Background Comparators that generate an output signal indicative of the result of the comparison by comparing input signals may be used in a variety of applications. For example, an analog-to-digital converter (ADC) for converting an analog signal into a digital signal may include a plurality of comparators, and generate the digital signal by encoding output signals from the plurality of comparators. For example, the switching regulator may include a comparator for comparing the feedback signal with a reference signal. The performance and efficiency of an application may depend on characteristics of the comparator, such as power consumption, operating speed, noise properties, area, accuracy, etc., and some characteristics of the comparator may be in a trade-off relationship. Therefore, it may be difficult to implement a comparator having better characteristics in all aspects. Disclosure of Invention At least one example embodiment of the present disclosure provides a comparison circuit capable of efficiently performing comparator offset calibration. At least one example embodiment of the present disclosure provides a method of operating a comparison circuit. According to an example embodiment, a comparison circuit includes a comparator and a multiplexer. The comparator includes at least one transistor and is configured to generate a first output signal based on the first input signal, the second input signal, and the operating clock signal. The multiplexer is configured to output a first clock signal as an operation clock signal based on the control signal in the normal mode, and to output a second clock signal different from the first clock signal as the operation clock signal based on the control signal in the offset calibration mode. In the offset calibration mode, the comparison circuit is configured to perform an offset calibration operation by degrading at least one transistor based on the first and second input signals having the same voltage level and the operation clock signal. According to an example embodiment, a method of operating a comparison circuit including at least one transistor includes determining whether an operation mode of the comparison circuit is an offset calibration mode or a normal mode, performing an offset calibration operation by degrading the at least one transistor based on first and second input signals having the same voltage level and an operation clock signal when the operation mode of the comparison circuit is the offset calibration mode, and performing a normal operation based on the first and second input signals having different voltage levels and the operation clock signal when the operation mode of the comparison circuit is the normal mode. According to an example embodiment, a comparison circuit includes a comparator and a multiplexer. The comparator includes at least one transistor and is configured to generate a first output signal based on the first input signal, the second input signal, and the operating clock signal. The multiplexer is configured to output a first clock signal as an operation clock signal based on the control signal in the normal mode, and to output a second clock signal different from the first clock signal as the operation clock signal based on the control signal in the offset calibration mode. The comparator includes a first p-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first n-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The first PMOS transistor and the second PMOS transistor are connected in parallel between a terminal to which a power supply voltage is applied and a terminal from which the first output signal is output. The first PMOS transistor includes a gate terminal connected to a terminal to which an operation clock signal is input. The second PMOS transistor includes a gate terminal connected to and outputting from the terminal of the second output signal. The third PMOS transistor and the fourth PMOS transistor are connected in parallel between a terminal to which the power supply voltage is applied and a terminal from which the second output signal is output. The third PMOS transistor includes a gate terminal connected to a termin