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CN-122001345-A - Method and device for generating jitter frequency clock signal

CN122001345ACN 122001345 ACN122001345 ACN 122001345ACN-122001345-A

Abstract

The application provides a method and a device for generating a frequency-jittering clock signal, and relates to the technical field of electronics. The method comprises the steps of obtaining target jitter frequency parameters comprising jitter frequency center frequency, jitter frequency modes and jitter frequency width, determining a modulation signal and a source clock signal according to the target jitter frequency parameters, enabling a first-order sigma-delta modulator to work in an unsaturated linear response area according to the amplitude change range of the modulation signal, inputting the modulation signal into the first-order sigma-delta modulator, performing pulse density modulation on the modulation signal by the first-order sigma-delta modulator under the driving of the source clock signal, outputting a unit pulse density modulation code stream, and performing edge detection on the unit pulse density modulation code stream to generate the jitter frequency clock signal. The technical scheme replaces a complex phase-locked loop circuit by a scheme which has a very simple structure and is completely realized by digital logic, and synchronously solves the balance problem of integration level, cost and signal purity.

Inventors

  • LI FEI

Assignees

  • 普冉半导体(上海)股份有限公司

Dates

Publication Date
20260508
Application Date
20260127

Claims (10)

  1. 1. The method for generating the frequency-jittered clock signal is characterized by comprising the following steps: obtaining a target jitter frequency parameter, wherein the target jitter frequency parameter comprises a jitter frequency center frequency, a jitter frequency mode and a jitter frequency width; Determining a modulation signal and a source clock signal according to the target jitter frequency parameter, wherein the amplitude of the modulation signal changes with time, and the amplitude change range is configured to enable a first-order Sigma-Delta modulator to work in a non-saturated linear response area; Inputting the modulation signal to a first-order Sigma-Delta modulator, and under the drive of the source clock signal, performing pulse density modulation on the modulation signal by the first-order Sigma-Delta modulator and outputting a unit pulse density modulation code stream; And carrying out edge detection on the unit pulse density modulation code stream to generate a frequency-jittering clock signal, wherein the instantaneous frequency of the frequency-jittering clock signal changes along with the amplitude change of the modulation signal.
  2. 2. The method of claim 1, wherein the modulated signal is generated by superimposing a periodically varying component with a randomly varying component, wherein the periodically varying component has a configurable amplitude, period, and offset, and wherein the randomly varying component has a configurable distribution range.
  3. 3. The method of claim 2, wherein the periodically varying component is a triangular wave signal.
  4. 4. The method of claim 2, wherein the amplitude variation of the modulated signal satisfies the relationship amp+bias+σ <1, wherein amp is the amplitude of the periodically varying component, bias is the offset of the periodically varying component, σ is the distribution of the randomly varying components [ - σ, σ ], and amp, bias, and σ are all numbers greater than zero.
  5. 5. The method of claim 2, wherein determining a modulated signal based on the target jitter parameter comprises: Determining the amplitude of the periodically-changing component according to the jitter frequency width; determining the period of the periodically-changing component according to the amplitude attenuation requirement of the jitter frequency center frequency; Determining the offset of the periodically-varying component according to the dithering frequency mode; And determining the distribution range of the randomness variation component according to the noise optimization requirement.
  6. 6. The method of claim 5, wherein the period of the periodically varying component, the jitter width, and the magnitude delta of the jitter center frequency satisfy the following relationship: wherein, the method comprises the steps of, Is the amplitude attenuation of the dither center frequency, In order to make the frequency jitter width be the same, Is the period of the periodically varying component.
  7. 7. The method of claim 1, wherein the amplitude of the modulated signal is configured to dynamically vary within an interval of [ -1, +1], the step of determining the modulated signal and the source clock signal based on the target jitter frequency parameter comprising: If the jitter frequency mode is the lower jitter frequency mode, determining that the frequency of the source clock signal is twice the jitter frequency center frequency, and setting the offset of the modulation signal to be 0; if the frequency-jittering mode is a double-sided frequency-jittering mode, determining that the frequency of the source clock signal is four times of the frequency-jittering center frequency, and setting the absolute value of the offset of the modulation signal to be 0.5; If the jitter mode is an upper jitter mode, determining that the frequency of the source clock signal is four times the jitter center frequency, and setting the offset of the modulation signal to be 0.
  8. 8. The method of claim 1, wherein the step of pulse density modulating the modulated signal by the first order Sigma-Delta modulator and outputting a unit pulse density modulated code stream comprises: Calculating an error between the modulation signal and a feedback value, wherein the feedback value is an initial value when iterating for the first time, and is a value determined according to the output of the last iteration when iterating for the non-first time; Accumulating the errors to obtain an accumulated value; Quantizing the accumulated value, outputting a first logic level as a current output when the accumulated value is greater than a first threshold value, outputting a second logic level as a current output when the accumulated value is less than a second threshold value, and forming the unit pulse density modulation code stream according to the current output; and determining a feedback value for the next iteration according to the current output.
  9. 9. The method of claim 1, wherein the mathematical expression of the instantaneous frequency of the dither clock signal as a function of the amplitude of the modulation signal is: , wherein, For dithering the instantaneous frequency of the clock signal, For the frequency of the source clock signal, Is the instantaneous amplitude of the modulated signal after normalization, and 。
  10. 10. A device for generating a jittered clock signal, comprising: The parameter access interface unit is configured to acquire target jitter frequency parameters, wherein the target jitter frequency parameters comprise jitter frequency center frequency, jitter frequency modes and jitter frequency width; A modulation signal generator unit configured to determine a modulation signal according to the target jitter frequency parameter, wherein the amplitude of the modulation signal changes with time, and the amplitude change range is configured to enable the first order Sigma-Delta modulator unit to work in a non-saturated linear response area; A clock source unit configured to provide a source clock signal according to the target jitter frequency parameter; a first order Sigma-Delta modulator unit configured to pulse density modulate the modulated signal under the drive of the source clock signal and output a unit pulse density modulated code stream; an edge detection unit configured to perform edge detection on the unit pulse density modulation code stream to generate a dither clock signal.

Description

Method and device for generating jitter frequency clock signal Technical Field The present application relates to the field of electronic technologies, and in particular, to a method and an apparatus for generating a jitter clock signal. Background A load such as a motor driven by pulse width modulation (Pulse Width Modulation, PWM) can generate significant electromagnetic interference (Electromagnetic Interference, EMI) during fast switching operations. In order to suppress electromagnetic interference, frequency jittering technology is widely adopted in the industry, that is, the frequency of a driving clock signal is regularly and slightly shifted around a set center frequency, so that concentrated frequency spectrum energy is diffused, and peak interference is reduced. Currently, the mainstream frequency-jittered clock signal generation scheme relies on a Phase-Locked Loop (PLL) circuit. This scheme typically employs a phase modulation function to control the PLL such that the frequency of its output signal fluctuates around a set center frequency following the phase modulation function. However, if an analog pll is adopted, passive components such as an external capacitor are usually required, which is not only unfavorable for high integration of the chip, but also increases system cost and physical area. If the full digital phase-locked loop is adopted, although an external analog element is avoided, the circuit structure is complex, frequency spurious and output time sequence jitter are easy to introduce in the frequency dynamic switching process, and therefore the quality and stability of a final output clock signal are affected. Therefore, the existing PLL-based jitter scheme is difficult to achieve a good balance in three key dimensions of chip integration, manufacturing cost, and output signal purity. Therefore, how to replace the conventional PLL scheme in a manner that the structure is simpler, the integration is easier, and the stable jittering clock signal can be output becomes a technical problem to be solved in the art. Disclosure of Invention The application aims to provide a method and a device for generating a jitter frequency clock signal, which can replace a complex phase-locked loop circuit by a scheme which has a very simple structure and is completely realized by digital logic, and synchronously solve the balance problem of integration level, cost and signal purity. The application is realized in the following way: The application provides a method for generating a jitter frequency clock signal, which comprises the following steps of obtaining target jitter frequency parameters, determining a modulation signal and a source clock signal according to the target jitter frequency parameters, wherein the amplitude of the modulation signal changes along with time, the amplitude change range of the modulation signal is configured to enable a first-order Sigma-Delta modulator to work in a non-saturated linear response area, inputting the modulation signal into the first-order Sigma-Delta modulator, and under the driving of the source clock signal, carrying out pulse density modulation on the modulation signal by the first-order Sigma-Delta modulator and outputting a unit pulse density modulation code stream, carrying out edge detection on the unit pulse density modulation code stream, and generating the jitter frequency clock signal, wherein the instantaneous frequency of the jitter frequency clock signal changes along with the amplitude change of the modulation signal. In a second aspect, the application provides a jitter frequency clock signal generating device, which comprises a parameter access interface unit, a modulation signal generator unit, a clock source unit and an edge detection unit, wherein the parameter access interface unit is configured to acquire target jitter frequency parameters, the target jitter frequency parameters comprise jitter frequency center frequency, jitter frequency mode and jitter frequency width, the modulation signal generator unit is configured to determine a modulation signal according to the target jitter frequency parameters, the amplitude of the modulation signal changes with time, the amplitude change range of the modulation signal is configured to enable a first-order Sigma-Delta modulator unit to work in a non-saturated linear response area, the clock source unit is configured to provide a source clock signal according to the target jitter frequency parameters, the first-order Sigma-Delta modulator unit is configured to perform pulse density modulation on the modulation signal under the driving of the source clock signal and output a unit pulse density modulation code stream, and the edge detection unit is configured to perform edge detection on the unit pulse density modulation code stream to generate the jitter frequency clock signal. Compared with the prior art, the application has at least the following advantages or beneficial effects: The app