CN-122001348-A - High-side NMOS (N-channel metal oxide semiconductor) driving circuit, chip and electronic equipment

CN122001348ACN 122001348 ACN122001348 ACN 122001348ACN-122001348-A

Abstract

The application provides a high-side NMOS drive circuit, a chip and electronic equipment, and relates to the technical field of power management chips, wherein the circuit comprises a system clock circuit, a local clock circuit, a pulse signal generating circuit, a multiplexing circuit, a charge pump circuit and a high-side NMOS transistor; the system clock circuit generates a system clock signal, the pulse signal generating circuit generates a pulse enabling signal according to a driving enabling signal, the local clock circuit outputs a high-frequency clock signal with the frequency larger than that of the system clock signal according to the pulse enabling signal, the multiplexing circuit outputs a target clock signal which is the system clock signal or the high-frequency clock signal according to the pulse enabling signal, and the charge pump circuit converts the battery voltage into a driving voltage according to the driving enabling signal and the target clock signal to drive the high-side NMOS transistor. The high-frequency clock signal with higher frequency is selected to control the charge pump circuit, so that the starting speed of the high-side NMOS tube can be improved.

Inventors

YANG RUI
CHEN JUNYU

Assignees

珠海楠欣半导体科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260123

Claims (10)

1. The high-side NMOS drive circuit is characterized by comprising a system clock circuit, a local clock circuit, a pulse signal generating circuit, a multiplexing circuit, a charge pump circuit and a high-side NMOS transistor; The system clock circuit comprises a multiplexing circuit, a charge pump circuit, a pulse signal generating circuit, a battery voltage, a high-side NMOS transistor, a battery voltage, a control terminal and a control terminal, wherein the output terminal of the system clock circuit is electrically connected with a first input terminal of the multiplexing circuit, the output terminal of the local clock circuit is electrically connected with a second input terminal of the multiplexing circuit, the enabling terminal of the charge pump circuit is electrically connected with the input terminal of the pulse signal generating circuit and is used for being connected with a driving enabling signal; The system clock circuit is used for generating a system clock signal; The pulse signal generating circuit is used for generating a pulse enabling signal according to the rising edge of the driving enabling signal; The local clock circuit is used for outputting a high-frequency clock signal according to the pulse enabling signal, wherein the frequency of the high-frequency clock signal is greater than that of the system clock signal; the multiplexing circuit is used for outputting a target clock signal according to the pulse enabling signal, wherein the target clock signal is the system clock signal or the high-frequency clock signal; The charge pump circuit is used for converting the battery voltage into a driving voltage according to the driving enabling signal and the target clock signal so as to drive the high-side NMOS transistor, wherein the driving voltage is larger than the battery voltage.
2. The high-side NMOS drive circuit according to claim 1, wherein the pulse signal generating circuit comprises a first NOT gate, a second NOT gate, a delay, a third NOT gate, and a first AND gate; The input end of the first NOT gate is used as the input end of the pulse signal generating circuit and is used for being connected with the driving enabling signal, the output end of the first NOT gate is electrically connected with the input end of the second NOT gate, and the output end of the second NOT gate is electrically connected with the input end of the delayer and the first input end of the first AND gate respectively; The output end of the delay device is electrically connected with the input end of the third NOT gate, the output end of the third NOT gate is electrically connected with the second input end of the first AND gate, and the output end of the first AND gate is used as the output end of the pulse signal generating circuit and used for outputting the pulse enabling signal.
3. The high-side NMOS drive circuit of claim 2, wherein a delay time of the delay device is equal to a pulse width duration of the pulse enable signal.
4. The high-side NMOS drive circuit of claim 3, wherein a pulse width duration of the pulse enable signal is greater than a drive rise time of the high-side NMOS transistor, wherein the drive rise time is a minimum time required to drive the high-side NMOS transistor in an on state.
5. The high-side NMOS drive circuit according to claim 1, wherein the charge pump circuit comprises a second AND gate and a voltage conversion circuit; The first input end of the second AND gate is electrically connected with the enabling end of the charge pump circuit and used for accessing the driving enabling signal, the second input end of the second AND gate is electrically connected with the control end of the charge pump circuit and used for accessing the target clock signal, and the output end of the second AND gate is electrically connected with the control end of the voltage conversion circuit; The input end of the voltage conversion circuit is used as the input end of the charge pump circuit and is used for being connected with the battery voltage, and the output end of the voltage conversion circuit is used as the output end of the charge pump circuit and is used for outputting the driving voltage; the second AND gate is used for performing AND logic operation on the received driving enabling signal and the target clock signal to obtain an input clock signal, and transmitting the input clock signal to the voltage conversion circuit; The voltage conversion circuit is used for converting the battery voltage into the driving voltage according to the input clock signal.
6. The high-side NMOS drive circuit of claim 5, wherein the input clock signal comprises a first input clock signal and a second input clock signal, and wherein the voltage conversion circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor; The first end of the first transistor is electrically connected with the first end of the second transistor and is used as an input end of the voltage conversion circuit for being connected with the battery voltage, and the second end of the first transistor is electrically connected with the second end of the third transistor, the first end of the first capacitor, the control end of the second transistor and the control end of the fourth transistor respectively; the control end of the first transistor is electrically connected with the control end of the third transistor, the second end of the second transistor, the second end of the fourth transistor and the first end of the second capacitor respectively; the first end of the third transistor is electrically connected with the first end of the fourth transistor and is used as an output end of the voltage conversion circuit for outputting the driving voltage; The second end of the first capacitor is used for being connected with the first input clock signal, and the second end of the second capacitor is used for being connected with the second input clock signal.
7. The high-side NMOS drive circuit according to claim 1, wherein said multiplexing circuit is configured to output said high-frequency clock signal when said pulse enable signal is high, and to output said system clock signal when said pulse enable signal is low.
8. The high-side NMOS drive circuit according to claim 7, wherein said local clock circuit is configured to output said high-frequency clock signal when said pulse enable signal is high, and to control itself to be in an off state when said pulse enable signal is low.
9. A chip comprising the system clock circuit, the local clock circuit, the pulse signal generating circuit, the multiplexing circuit and the charge pump circuit according to any one of claims 1 to 8.
10. An electronic device comprising a chip as claimed in claim 9.

Description

High-side NMOS (N-channel metal oxide semiconductor) driving circuit, chip and electronic equipment Technical Field The present application relates to the field of power management chips, and in particular, to a high-side NMOS driving circuit, a chip, and an electronic device. Background An NMOS (N-CHANNEL METAL Oxide Semiconductor FIELD EFFECT Transistor) is a field effect Transistor, which is generally used as a switch to control the NMOS Transistor to be in an on state or an off state by driving the gate of the NMOS Transistor. In one example, the NMOS transistor is in an on state when the voltage difference between the gate and the source of the NMOS transistor (i.e., the gate-source voltage Vgs) is greater than the threshold voltage Vth of the NMOS transistor, and is in an off state when the voltage difference between the gate and the source of the NMOS transistor (i.e., the gate-source voltage Vgs) is less than the threshold voltage Vth of the NMOS transistor. Referring to fig. 1, fig. 1 is a schematic circuit diagram of a high-side NMOS driving circuit provided in the related art, as shown in fig. 1, the high-side NMOS driving circuit is applied to a high-side driving lithium battery protection chip, and the lithium battery protection chip generally includes a driving end pin_d, and the driving end pin_d is electrically connected to a gate of an NMOS transistor (Mload in fig. 1) outside the chip to drive an NMOS transistor Mload outside the chip. Since the NMOS transistor Mload outside the chip is provided on the high-voltage side, it is generally called a high-side NMOS transistor, and when the high-side NMOS transistor Mload is used as a switch, the high-side NMOS transistor Mload is also called a charge switch transistor or a discharge switch transistor, and the source and the drain thereof are used to connect different objects, respectively. In one example, if the high side NMOS tube Mload is used as a charging switch, the source may be electrically connected to the battery, the drain may be correspondingly electrically connected to the adapter, when the high side NMOS tube Mload is turned on, the current Iload flowing through the high side NMOS tube is provided through the adapter to charge the battery, and if the high side NMOS tube Mload is used as a discharging switch, the drain may be electrically connected to the battery, the source may be correspondingly electrically connected to the load, when the high side NMOS tube Mload is turned on, the current Iload flowing through the high side NMOS tube Mload is provided through the battery, and the load is discharged through the battery. Referring to fig. 1, fig. 1 shows an application scenario in which a high-side NMOS transistor is used as a charging switch transistor, and a source electrode of the high-side NMOS transistor Mload is electrically connected to a battery, and a drain electrode is electrically connected to an adapter. In this scenario, if the high-side NMOS transistor Mload is to be turned on, a control voltage v_drv needs to be provided to the gate of the high-side NMOS transistor Mload, and the difference between the control voltage v_drv and the battery-side voltage v_bat is greater than the threshold voltage Vth of the high-side NMOS transistor Mload. The chip comprises a clock circuit and a charge pump, wherein the clock circuit is an internal clock of a lithium battery protection chip and is used for outputting a clock signal CLK1, the clock signal CLK1 is generally used for delaying and timing protection events such as overvoltage, overcurrent and the like, the frequency of the clock signal CLK1 is generally of the order of KHz, the charge pump is a voltage doubling circuit and is used for boosting an accessed battery side voltage V_BAT, the battery side voltage V_BAT which is 2 times can be obtained, and the voltage is transmitted to the grid electrode of the high-side NMOS tube Mload and used as a control voltage V_DRV to drive the high-side NMOS tube Mload. Referring to fig. 1, when the high-side NMOS transistor Mload is used as a charge switch or a discharge switch, the current flowing through itself is generally in ampere level and is in a larger magnitude, so that the NMOS transistor Mload outside the chip needs to have a larger size to meet the overcurrent capability, which also causes the input parasitic capacitance (equivalent to the parasitic capacitance Cload) of the high-side NMOS transistor Mload to be in nF level, and when the high-side NMOS transistor Mload is started, the parasitic capacitance Cload is equivalently charged by the control voltage v_drv until the gate voltage of the high-side NMOS transistor Mload is charged to a sufficiently high voltage. If the turn-on speed of the high-side NMOS transistor Mload is required to be fast enough, it means that the control voltage v_drv is required to provide a sufficiently large charging current, and the amount of charge that can be pumped out at a time is consta