CN-122001352-A - Switching circuit exceeding voltage withstand condition of element

Abstract

The invention provides a switching circuit exceeding a voltage withstand condition of an element, which comprises a biasing circuit, at least one first transistor, a plurality of second transistors and a third transistor. The bias circuit includes a plurality of bias elements connected in series with each other and coupled to a voltage source to form a plurality of voltage drop nodes through the bias elements. The second transistors are connected in series and coupled to a voltage source, and are coupled to the voltage drop nodes one to one. A first transistor is provided between any two adjacent ones of the second transistors. The third transistor is connected with the second transistors in series to form a switch path. When the third transistor receives a control signal to be turned on, the first transistors are turned off and the second transistors are turned on, so that the switch path is turned on.

Inventors

• ZHU LICHENG

Assignees

• 瑞昱半导体股份有限公司

Dates

Publication Date

20260508

Application Date

20241104

Claims (10)

1. 1. A switching circuit that overrides a voltage withstand condition of an element, comprising: a bias circuit including a plurality of bias elements connected in series with each other and coupled to a voltage source to form a plurality of voltage drop nodes via the plurality of bias elements; at least one first transistor; A plurality of second transistors connected in series with each other and coupled to the voltage source and coupled one-to-one to the plurality of voltage drop nodes, the first transistor being disposed between any two adjacent ones of the plurality of second transistors, and A third transistor connected in series with the second transistors to form a switch path and located at a low voltage side of the second transistors; when the third transistor receives a control signal to be turned on, the first transistors are turned off and the second transistors are turned on, so that the switch path is turned on; When the third transistor receives the control signal and is turned off, the first transistors are turned on and the second transistors are turned off, so that the switch path is turned off.
2. 2. The switch circuit of claim 1, wherein each of the first transistors is a P-type metal oxide semiconductor transistor and has a first gate, a first source and a first drain.
3. 3. The switch circuit of claim 1, wherein each of the second transistors is a deep N-well N-type mos transistor and has a second gate, a second source and a second drain, the second gate being coupled to the corresponding voltage drop node.
4. 4. The switch circuit of claim 3, wherein each of said first transistors is a P-type metal oxide semiconductor transistor and has a first gate, a first source and a first drain, said second gate and said second drain of said second transistor adjacent to said low voltage side to which each of said first transistors is coupled are respectively coupled to said first gate and said first drain of said first transistor, and said second gate of said second transistor remote from said low voltage side to which each of said first transistors is coupled to said first source of said first transistor.
5. 5. The switching circuit of claim 4 wherein, in any two adjacent ones of the plurality of second transistors, the second drain of the second transistor adjacent to the low voltage side is coupled away from the second source of the second transistor on the low voltage side.
6. 6. The switch circuit of claim 5, wherein the third transistor is an N-type mos transistor and has a third gate, a third source and a third drain, the third gate receiving the control signal, the third source being coupled to ground, the third drain being coupled to the second source of the second transistor to which the third transistor is coupled.
7. 7. The switching circuit of claim 1, wherein the switching path further comprises a pull-down resistor coupled between the voltage source and a high voltage side of the plurality of second transistors.
8. 8. The switching circuit for exceeding a voltage withstand condition of a device according to claim 1, wherein the plurality of bias devices are a plurality of resistors connected in series.
9. 9. The switching circuit of claim 1, wherein the plurality of biasing elements are a plurality of diodes in series that are forward biased from the voltage source.
10. 10. The switch circuit of claim 1, wherein the plurality of bias devices are a plurality of fourth transistors in series, wherein the fourth transistors are N-type mos transistors and have a fourth gate, a fourth source and a fourth drain, the fourth drain being coupled to the fourth gate and to the fourth source of the fourth transistor adjacent thereto.

Description

Switching circuit exceeding voltage withstand condition of element Technical Field The present invention relates to a switching circuit, and more particularly, to a switching circuit exceeding a voltage withstand condition of an element. Background The recent circuit design is biased to use advanced processes, and although the design can achieve area advantage, the voltage withstand of the electronic component of the advanced process is smaller, so that the circuit is difficult to be applied to the traditional analog circuit. For a 6nm process, the switching element has only 1.8V withstand voltage, which is difficult to apply to a 5V (e.g., USB power supply circuit). Disclosure of Invention In view of the above, an embodiment of the present invention provides a switching circuit that exceeds a voltage withstanding condition of a device, including a bias circuit, at least a first transistor, a plurality of second transistors, and a third transistor. The bias circuit includes a plurality of bias elements connected in series with each other and coupled to a voltage source to form a plurality of voltage drop nodes through the bias elements. The second transistors are connected in series and coupled to a voltage source, and are coupled to the voltage drop nodes one to one. A first transistor is provided between any two adjacent ones of the second transistors. The third transistor is connected in series with the second transistors to form a switch path and is positioned on a low voltage side of the second transistors. When the third transistor receives a control signal to be turned on, the first transistors are turned off and the second transistors are turned on, so that the switch path is turned on, and when the third transistor receives the control signal to be turned off, the first transistors are turned on and the second transistors are turned off, so that the switch path is turned off. According to the switching circuit of the overrunning element voltage-withstanding condition according to some embodiments of the present invention, the bias elements of the bias circuit are serially layered, so that each layer of elements can perform switching control within the voltage-withstanding section thereof, thereby achieving the switching circuit operating under the operating voltage of the overrunning element voltage-withstanding condition. In addition, since only one control signal needs to be fed in to control the switching circuit, the situation that a plurality of control signals possibly generate signal delay to cause transient overvoltage of the element is avoided. Drawings FIG. 1 is a schematic diagram of a switch circuit for withstand voltage conditions of an overdrive device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a bias circuit according to another embodiment of the invention. FIG. 3 is a schematic diagram of a bias circuit according to another embodiment of the invention. Fig. 4 is a schematic diagram of an equivalent switching circuit according to an embodiment of the invention. Fig. 5 is a schematic structural diagram of a third transistor according to an embodiment of the invention. Fig. 6 is a schematic structural diagram of a second transistor according to an embodiment of the invention. Fig. 7 is a schematic diagram illustrating a switch path according to an embodiment of the invention. Fig. 8 is a schematic diagram of a switch path turn-off according to an embodiment of the invention. Fig. 9 is a schematic diagram of a switch circuit for applying the withstand voltage condition of the override device to the USB protocol according to an embodiment of the present invention. Reference numerals illustrate: 100 is a switching circuit 200 exceeding the withstand voltage condition of the device, a source device 300 and a drain device 300 400 Configuration channel detector B body BC bias circuit CC1, CC2 are arranged with channel pins D, drains D1-D6, diodes M, M1 to M6 fourth transistor G is gate DNW deep N well Nd, nd 1-Nd 3, second transistor PSUB, substrate Me, equivalent switch P, P1, P2 first transistor PW P-well N third transistor R1 to R3, rx: resistor R4, grounding resistor Rd, pull-down resistor VA, VB, VC, voltage drop node S, source Rt, switch path VD, VE, VF, VG, VH, VI node Vdd, voltage source Se, control signal Detailed Description As used herein, "coupled" refers to two or more elements being in "direct" physical or electrical contact with each other, or in "indirect" physical or electrical contact with each other. Referring to fig. 1, a schematic diagram of a switching circuit 100 for withstanding voltage conditions of an overdrive device according to an embodiment of the present invention is shown. The switching circuit 100 exceeding the withstand voltage condition of the device includes a bias circuit BC, at least a first transistor P, a plurality of second transistors Nd and a third transistor N. Here, two first transistors P (P1, P2) and th