CN-122001356-A - Grid voltage bootstrapping switch circuit applied to pipeline successive approximation type ADC

CN122001356ACN 122001356 ACN122001356 ACN 122001356ACN-122001356-A

Abstract

The invention belongs to the field of analog integrated circuit calculation, and particularly relates to a grid voltage bootstrap switch circuit applied to a pipeline successive approximation type ADC (analog to digital converter), wherein the working mode of the grid voltage bootstrap switch circuit is divided into two states of sampling and holding and is respectively controlled by two non-overlapping clocks of CLK and CLKB, when CLK is high level and CLKB is low level, the grid voltage bootstrap switch is in a holding state, the output voltage VOUT is kept unchanged, otherwise, when CLK is low level and CLKB is high level, the grid voltage bootstrap switch is in a sampling state, and the output voltage VOUT changes along with the change of an input signal VIN. The circuit reduces the area of the traditional grid voltage bootstrap switch, effectively reduces the parasitic capacitance of the grid electrode of the sampling input tube, and improves the linearity and the speed of the grid voltage bootstrap switch on the whole.

Inventors

TANG HE
LI JUNJIANG
CHEN LEI
PENG XIZHU

Assignees

重庆邮电大学
电子科技大学重庆微电子产业技术研究院

Dates

Publication Date: 20260508
Application Date: 20260121

Claims (4)

1. The gate voltage bootstrapping switch circuit applied to the pipeline successive approximation type ADC is characterized by comprising transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11 and M12, a sampling capacitor Cs, a bootstrapping capacitor Cb and an inverter INV; The clock control signal CLK is connected with the input end of the inverter INV, the grid electrode of the transistor M2, the grid electrode of the transistor M9 and the grid electrode of the transistor M12; The grid electrode of the transistor M1 is connected with the drain electrodes of the transistor M5 and the transistor M8 and the grid electrode of the transistor M10, the source electrode of the transistor M1 is connected with the source electrode of the transistor M3, the grid electrode of the transistor M8 and the power supply voltage VDD, and the drain electrode of the transistor M1 is connected with the upper polar plate of the bootstrap capacitor Cb, the source electrode of the transistor M5 and the source electrode of the transistor M6; the drain electrode of the transistor M2 is connected with the lower polar plate of the bootstrap capacitor Cb, the source electrode of the transistor M4 and the source electrode of the transistor M7, and the source electrode of the transistor M2 is grounded; The output end of the inverter INV outputs a clock control signal CLKB and is connected with the grid electrode of the transistor M3 and the grid electrode of the transistor M4, and the drain electrode of the transistor M3 is connected with the drain electrode of the transistor M4, the grid electrode of the transistor M5 and the grid electrode of the transistor M6; the drain electrode of the transistor M6 is connected with the gate electrode of the transistor M7 and the drain electrode of the transistor M11; the drain electrode of the transistor M7 is connected with the source electrode of the transistor M10 and the signal input end VIN; The source electrode of the transistor M8 is connected with the drain electrode of the transistor M9; The source electrode of the transistor M9 is grounded; The drain electrode of the transistor M10 and the upper polar plate of the sampling capacitor Cs are connected to be used as an output signal end VOUT; The lower polar plate of the sampling capacitor Cs is grounded; the grid electrode of the transistor M11 is connected with the power supply voltage VDD, and the source electrode of the transistor M11 is connected with the drain electrode of the transistor M12; the source of transistor M12 is grounded.
2. The gate voltage bootstrapped switch circuit applied to a pipeline successive approximation ADC as claimed in claim 1, wherein the transistor M10 is a main switch transistor, and the remaining transistors and capacitors are auxiliary devices.
3. The gate voltage bootstrapped switch circuit for use in a pipeline successive approximation ADC of claim 1, wherein the gate voltage bootstrapped switch circuit is configured to operate in two states, sample and hold, respectively controlled by two non-overlapping clocks, CLK and CLKB.
4. The gate bootstrapped switch circuit of claim 3, wherein when CLK is high and CLKB is low, the gate bootstrapped switch is in a hold state, and the output voltage VOUT is kept unchanged, whereas when CLK is low and CLKB is high, the gate bootstrapped switch is in a sample state, and the output voltage VOUT changes along with the change of the input signal VIN.

Description

Grid voltage bootstrapping switch circuit applied to pipeline successive approximation type ADC Technical Field The invention belongs to the field of analog integrated circuit calculation, and particularly relates to a gate voltage bootstrap switch circuit applied to a pipeline successive approximation type ADC. Background Analog-to-digital converters (ADCs) are devices that convert continuous analog signals into discrete digital signals and then provide the digital signals to electronic devices for processing operations. With the rapid development of communication technology, modern electronic systems put higher demands on the conversion speed and accuracy of ADCs. In various ADC architectures, pipeline successive approximation type ADC (Pipeline SAR ADC) has been widely focused and applied because of its capability of realizing high-speed and high-precision conversion performance under lower power consumption and smaller chip area. The sample/hold circuit is a critical module of the pipeline successive approximation type ADC, the position of the sample/hold circuit is the forefront end of the signal input, the input signal is directly processed, the performance of the sample/hold circuit directly influences the overall linearity and the dynamic range of the system, and the sampling switch is a core component for determining the sampling precision and the signal integrity. The traditional sampling switch mostly adopts a single MOS tube or CMOS transmission gate structure, and the on-resistance changes along with the input signal level, so that nonlinear distortion is introduced in the sampling process, and the requirement of high-precision ADC on the alignment cannot be met. In order to improve the linearity problem of the switch, a grid voltage bootstrap switch is widely adopted, and the grid source voltage of a switch tube is kept constant through a bootstrap capacitor structure, so that the on-resistance of the switch tube is not related to an input signal, and the sampling linearity and speed are improved. However, conventional gate voltage bootstrap switches still have many limitations in practical applications. Firstly, a voltage multiplication structure is often used in the bootstrap circuit, and a plurality of capacitors and MOS transistors are needed to be relied on, so that larger chip area consumption can be caused. Secondly, in a traditional grid voltage bootstrap switch, the grid electrode of a sampling input tube is connected with the grid electrodes and the drain electrodes of a plurality of MOS tubes, so that the parasitic capacitance of the grid electrode of the switching tube is overlarge, and the sampling speed and the sampling precision are reduced. Disclosure of Invention In order to solve the technical problems, the invention provides a gate voltage bootstrap switch circuit applied to a pipeline successive approximation type ADC, which comprises transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11 and M12, a sampling capacitor Cs, a bootstrap capacitor Cb and an inverter INV; The clock control signal CLK is connected with the input end of the inverter INV, the grid electrode of the transistor M2, the grid electrode of the transistor M9 and the grid electrode of the transistor M12; The grid electrode of the transistor M1 is connected with the drain electrodes of the transistor M5 and the transistor M8 and the grid electrode of the transistor M10, the source electrode of the transistor M1 is connected with the source electrode of the transistor M3, the grid electrode of the transistor M8 and the power supply voltage VDD, and the drain electrode of the transistor M1 is connected with the upper polar plate of the bootstrap capacitor Cb, the source electrode of the transistor M5 and the source electrode of the transistor M6; the drain electrode of the transistor M2 is connected with the lower polar plate of the bootstrap capacitor Cb, the source electrode of the transistor M4 and the source electrode of the transistor M7, and the source electrode of the transistor M2 is grounded; The output end of the inverter INV outputs a clock control signal CLKB and is connected with the grid electrode of the transistor M3 and the grid electrode of the transistor M4, and the drain electrode of the transistor M3 is connected with the drain electrode of the transistor M4, the grid electrode of the transistor M5 and the grid electrode of the transistor M6; the drain electrode of the transistor M6 is connected with the gate electrode of the transistor M7 and the drain electrode of the transistor M11; the drain electrode of the transistor M7 is connected with the source electrode of the transistor M10 and the signal input end VIN; The source electrode of the transistor M8 is connected with the drain electrode of the transistor M9; The source electrode of the transistor M9 is grounded; The drain electrode of the transistor M10 and the upper polar plate of the sampling capacitor Cs are connected to be use