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CN-122001360-A - Multiplexer circuit for battery management system and corresponding battery management system

CN122001360ACN 122001360 ACN122001360 ACN 122001360ACN-122001360-A

Abstract

The present disclosure relates to a multiplexer circuit for a battery management system and a corresponding battery management system. The MUX for the battery management system includes first, second and third input terminals for coupling to first, second and third ones of the battery stacks, respectively. The first, second and third switches have respective first, second and third terminals coupled to the first, second and third input terminals of the MUX, respectively. The AFE and selection circuit includes first, second and third input terminals coupled to the second terminals of the first, second and third switches, respectively, first and third output terminals for coupling to the positive inputs of the first and second level shifter circuits, and second and fourth output terminals for coupling to the negative inputs of the first and second level shifter circuits, respectively. Each of the first, second, third and fourth output terminals of the AFE and selection circuit is selectively coupleable to any one of the first, second and third input terminals of the AFE and selection circuit.

Inventors

  • C. Kurina
  • V. Ben Doty
  • A. Mazioli

Assignees

  • 意法半导体国际公司

Dates

Publication Date
20260508
Application Date
20251024
Priority Date
20241107

Claims (20)

  1. 1. A multiplexer circuit MUX for a battery management system, the MUX comprising: The battery pack comprises a first input terminal configured to be coupled to a first pin of a battery stack, a second input terminal configured to be coupled to a second pin of the battery stack, and a third input terminal configured to be coupled to a third pin of the battery stack; A first switch having a respective first terminal coupled to a first input terminal of the MUX, a second switch having a respective first terminal coupled to a second input terminal of the MUX, and a third switch having a respective first terminal coupled to a third input terminal of the MUX, and An analog front end AFE and selection circuit comprising: a first input terminal coupled to a second terminal of the first switch; A second input terminal coupled to a second terminal of the second switch; a third input terminal coupled to a second terminal of the third switch; A first output terminal configured to be coupled to a positive input of a first level shifter circuit; A second output terminal configured to be coupled to a negative input of the first level shifter circuit; a third output terminal configured to be coupled to the positive input of the second level shifter circuit, and A fourth output terminal configured to be coupled to a negative input of the second level shifter circuit; Wherein each of the first, second, third and fourth output terminals of the AFE and selection circuit is selectively coupleable to any of the first, second and third input terminals of the AFE and selection circuit.
  2. 2. The multiplexer circuit of claim 1, wherein the AFE and select circuit comprises: A first 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the first output terminal of the AFE and selection circuit; a second 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the second output terminal of the AFE and selection circuit; A third 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the third output terminal of the AFE and selection circuit, and A fourth 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the fourth output terminal of the AFE and selection circuit.
  3. 3. The multiplexer circuit of claim 1, wherein the AFE and selection circuit comprises a first selector, a second selector, a third selector, and a fourth selector, wherein each selector has a respective first input and second input and a respective first output and second output, wherein any output of each selector is selectively coupleable to any input of the same selector, and wherein: a first input of the first selector is connected to a first input terminal of the AFE and selection circuit; a second input of the first selector is connected to a second input terminal of the AFE and selection circuit; a first input of the second selector is connected to a second input terminal of the AFE and selection circuit; A second input of the second selector is connected to a third input terminal of the AFE and selection circuit; A first input of the third selector is connected to a first output of the first selector; A second input of the third selector is connected to a first output of the second selector; a first input of the fourth selector is connected to a second output of the first selector; a second input of the fourth selector is connected to a second output of the second selector; A first output terminal of the third selector is connected to a positive input terminal of the first level shifter circuit; A second output terminal of the third selector is connected to a negative input terminal of the first level shifter circuit; a first output terminal of the fourth selector is connected to the positive input terminal of the second level shifter circuit, and A second output of the fourth selector is connected to a negative input of the second level shifter circuit.
  4. 4. The multiplexer circuit of claim 1, wherein each of the first, second, and third switches comprises a first transistor and a second transistor having respective conductive channels arranged in series between an input terminal and an output terminal of the switch.
  5. 5. The multiplexer circuit of claim 4, wherein in each of the first, second, and third switches, the first transistor comprises an n-channel Metal Oxide Semiconductor (MOS) transistor having a drain terminal coupled to an input terminal of the switch, a source terminal coupled to a common node, and a gate terminal coupled to a select node, and the second transistor comprises an n-channel MOS transistor having a drain terminal coupled to an output terminal of the switch, a source terminal coupled to the common node, and a gate terminal coupled to the select node.
  6. 6. The multiplexer circuit of claim 5, wherein each of the first, second, and third switches comprises: A current source coupled between a power rail and the select node and configured to provide current to the select node, and A resistor and a third transistor arranged in series between the select node and ground.
  7. 7. The multiplexer circuit of claim 6, wherein in each of the first, second, and third switches, the third transistor comprises a p-channel MOS transistor having a drain terminal coupled to ground, a source terminal coupled to a respective resistor, and a gate terminal coupled to the common node.
  8. 8. The multiplexer circuit of claim 5, wherein each of the first, second, and third switches comprises a diode having an anode terminal coupled to the select node and a cathode terminal coupled to a bias node.
  9. 9. A multiplexer circuit according to claim 3, wherein each of the first and second selectors comprises: A current source coupled between a power rail and a bias node and configured to provide a first current to the bias node; A zener diode having an anode terminal coupled to the further bias node and a cathode terminal coupled to the bias node; A fourth transistor and a fifth transistor having respective conductive channels arranged in parallel between the further bias node and the floating ground node, wherein a control terminal of the fourth transistor is connected to the first input node of the selector and a control terminal of the fifth transistor is connected to the second input node of the selector, and A further current source coupled between the floating ground node and ground and configured to sink a second current from the floating ground node.
  10. 10. The multiplexer circuit of claim 9, wherein each of the first and second selectors comprises a transmission gate block coupled between two inputs of the selector and two outputs of the selector and comprising one or more CMOS transmission gates to selectively couple any output of the selector to any input of the selector.
  11. 11. The multiplexer circuit of claim 10, wherein each of the first and second selectors comprises: A sixth transistor having a conductive channel disposed between the power rail and a secondary power supply node and a control terminal coupled to the bias node, and A second zener diode having an anode terminal coupled to the floating ground node and a cathode terminal coupled to the secondary supply node; Wherein the transmission gate block is biased between the secondary supply node and the floating ground node.
  12. 12. The multiplexer circuit of claim 1, comprising: a fourth input terminal configured to be coupled to ground, and a fifth input terminal configured to be coupled to a universal input pin, and A fourth switch having a respective first terminal coupled to the fourth input terminal of the MUX, and a fifth switch having a respective first terminal coupled to the fifth input terminal of the MUX; Wherein a first input terminal of the AFE and selection circuit is coupled to a second terminal of the fourth switch and a second input terminal of the AFE and selection circuit is coupled to a second terminal of the fifth switch.
  13. 13. The multiplexer circuit of claim 1, comprising: A sixth input terminal configured to be coupled to a reference pin, and A sixth switch having a respective first terminal coupled to a sixth input terminal of the MUX; Wherein a second input terminal of the AFE and selection circuit is coupled to a second terminal of the sixth switch.
  14. 14. A battery management system, comprising: A multiplexer circuit MUX comprising: The battery pack comprises a first input terminal configured to be coupled to a first pin of a battery stack, a second input terminal configured to be coupled to a second pin of the battery stack, and a third input terminal configured to be coupled to a third pin of the battery stack; A first switch having a respective first terminal coupled to a first input terminal of the MUX, a second switch having a respective first terminal coupled to a second input terminal of the MUX, and a third switch having a respective first terminal coupled to a third input terminal of the MUX, and An analog front end AFE and selection circuit comprising: a first input terminal coupled to a second terminal of the first switch; A second input terminal coupled to a second terminal of the second switch; a third input terminal coupled to a second terminal of the third switch; A first output terminal configured to be coupled to a positive input of a first level shifter circuit; A second output terminal configured to be coupled to a negative input of the first level shifter circuit; a third output terminal configured to be coupled to the positive input of the second level shifter circuit, and A fourth output terminal configured to be coupled to a negative input of the second level shifter circuit; wherein each of the first, second, third and fourth output terminals of the AFE and selection circuit is selectively coupleable to any of the first, second and third input terminals of the AFE and selection circuit; a first level shifter circuit having a positive input coupled to a first output terminal of the AFE and selection circuit, a negative input coupled to a second output terminal of the AFE and selection circuit, and an output port; A second level shifter circuit having a positive input coupled to the third output terminal of the AFE and selection circuit, a negative input coupled to the fourth output terminal of the AFE and selection circuit, and an output port; a first analog-to-digital converter ADC circuit having an input port coupled to an output port of the first level shifter circuit, and A second ADC circuit having an input port coupled to the output port of the second level shifter circuit.
  15. 15. The battery management system of claim 14 wherein the third pin of the stack is connected to the anode terminal of an odd numbered cell of the stack, the second pin of the stack is connected to the cathode terminal of an odd numbered cell of the stack and to the anode terminal of a subsequent even numbered cell of the stack, and the first pin of the stack is connected to the cathode terminal of a subsequent even numbered cell of the stack.
  16. 16. The battery management system of claim 14 wherein the AFE and selection circuit comprises: A first 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the first output terminal of the AFE and selection circuit; a second 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the second output terminal of the AFE and selection circuit; A third 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the third output terminal of the AFE and selection circuit, and A fourth 4:1 MUX having three inputs coupled to the first, second and third input terminals of the AFE and selection circuit, respectively, and having one output coupled to the fourth output terminal of the AFE and selection circuit.
  17. 17. The battery management system of claim 14 wherein the AFE and selection circuit comprises a first selector, a second selector, a third selector, and a fourth selector, wherein each selector has a respective first and second input and a respective first and second output, wherein any output of each selector is selectively coupleable to any input of the same selector, and wherein: a first input of the first selector is connected to a first input terminal of the AFE and selection circuit; a second input of the first selector is connected to a second input terminal of the AFE and selection circuit; a first input of the second selector is connected to a second input terminal of the AFE and selection circuit; A second input of the second selector is connected to a third input terminal of the AFE and selection circuit; A first input of the third selector is connected to a first output of the first selector; A second input of the third selector is connected to a first output of the second selector; a first input of the fourth selector is connected to a second output of the first selector; a second input of the fourth selector is connected to a second output of the second selector; A first output terminal of the third selector is connected to a positive input terminal of the first level shifter circuit; A second output terminal of the third selector is connected to a negative input terminal of the first level shifter circuit; a first output terminal of the fourth selector is connected to the positive input terminal of the second level shifter circuit, and A second output of the fourth selector is connected to a negative input of the second level shifter circuit.
  18. 18. The battery management system of claim 14 wherein each of the first, second, and third switches comprises first and second transistors having respective conductive channels arranged in series between an input terminal and an output terminal of the switch.
  19. 19. The battery management system of claim 14, wherein the MUX comprises: a fourth input terminal configured to be coupled to ground, and a fifth input terminal configured to be coupled to a universal input pin, and A fourth switch having a respective first terminal coupled to the fourth input terminal of the MUX, and a fifth switch having a respective first terminal coupled to the fifth input terminal of the MUX; Wherein a first input terminal of the AFE and selection circuit is coupled to a second terminal of the fourth switch and a second input terminal of the AFE and selection circuit is coupled to a second terminal of the fifth switch.
  20. 20. The battery management system of claim 14, wherein the MUX comprises: A sixth input terminal configured to be coupled to a reference pin, and A sixth switch having a respective first terminal coupled to a sixth input terminal of the MUX; Wherein a second input terminal of the AFE and selection circuit is coupled to a second terminal of the sixth switch.

Description

Multiplexer circuit for battery management system and corresponding battery management system Cross Reference to Related Applications The present application claims the benefit of italian patent application No. 102024000025068 filed at 7, 11, 2024, which is incorporated herein by reference. Technical Field The present description relates to a multiplexer circuit (MUX) that may be used in a Battery Management System (BMS), in particular for coupling pins of a stack of battery cells (a stack of battery cells) to input terminals of a set of analog-to-digital converters (ADCs) of the BMS. Background A battery management system is an electronic device or system configured to monitor and/or control a rechargeable battery. For example, the BMS may be configured to control the battery such that it does not operate outside its Safe Operating Area (SOA), and/or monitor the state of the battery by running certain diagnostic processes. Batteries that may be coupled to the BMS may include, for example, high voltage (e.g., 400V or 800V) battery packs (battery packs) for pure electric vehicles (BEV) or hybrid electric vehicles (HEV and PHEV), medium voltage (e.g., 48V) battery packs for Mild Hybrid Electric Vehicles (MHEV), batteries for backup energy storage systems and Uninterruptible Power Supplies (UPS), and the like. The function of the BMS device is to measure the voltage of each battery cell within a stack of cells (i.e., a plurality of cells connected in series) of a battery or a battery pack so as to be able to perform some internal functions such as charge balancing, diagnosis, temperature sensing, and other functions. Typically, each of the n cells in the stack must be selectively connectable to a dedicated ADC circuit due to timing requirements. In this regard, reference may be made to fig. 1, which is a circuit block diagram illustrating a possible arrangement of a battery B coupled to a BMS 10. Battery B includes a stack of n series-coupled battery cells, from a "lowest" (or first) Cell 1 to a "highest" (or nth) Cell n. the anode terminal of the first Cell 1 is coupled to ground GND and its cathode terminal is coupled to the anode terminal of the second Cell 2, the anode terminal of each intermediate Cell (from Cell 2 to Cell n-1) is coupled to the cathode terminal of the previous Cell and its cathode terminal is coupled to the anode terminal of the next Cell, and the anode terminal of the last Cell n is coupled to the cathode terminal of the previous Cell n-1 and its cathode terminal is coupled to the topmost pin of the stack (battery stack) which provides the maximum output voltage of the stack. The stack has n+1 pins, including pin C 0 coupled to ground, and pins C 1 to C n each coupled to the cathode terminal of a corresponding Cell (i.e., cell 1 to Cell n). The BMS 10 includes an analog multiplexer circuit 12 having n+1 input terminals, each input terminal coupled to a respective one of the pins C 0 through C n of the stack, and n pairs of output terminals, each pair of output terminals coupled to an input port of a respective ADC circuit 14. The ADC circuits 14 1 to 14 n generate corresponding digital output signals (e.g., multi-bit signals) bs 1 to bs n. Due to the typical rated voltage of battery B, MUX 12 may be designed to withstand an absolute maximum voltage of up to about 100V pin-to-pin and pin-to-ground. For a better understanding of the connections that may be made by MUX 12, reference may be made to fig. 2, which is a circuit block diagram showing in detail the architecture of MUX 12, which is implemented to connect the pins of two consecutive cells (common odd Cell i-1 and common even Cell i) to respective ADCs 14 i-1 and 14 i. It will be appreciated that the architecture of fig. 2 may be replicated in MUX 12 for each pair of consecutive battery cells (each pair including odd and even cells, e.g., cell 1 and Cell 2、Cell3 and Cell 4, up to Cell n-1 and Cell n). By looking at fig. 2, it will be noted that each input terminal of each ADC (i.e. both the positive and negative input terminals) should be selectively coupleable to both the cathode and anode of the respective battery cell via dedicated switches so that each ADC in the universal position j can read the voltage of the corresponding battery cell in position j while also allowing the chopping function to be performed, for which eight switches must be implemented. Furthermore, for safety reasons, the possibility of implementing a switching function is often required, allowing each odd-numbered ADC (e.g. 14 i-1) to read the voltage of the corresponding even-numbered Cell (e.g. Cell i) in the same pair and each even-numbered ADC (e.g. 14 i) to read the voltage of the corresponding odd-numbered Cell (e.g. Cell i-1) in the same pair, meaning that each input terminal (i.e. both positive and negative input terminals) of each odd-numbered ADC should also be selectively coupleable to the cathode of the corresponding even-numbered