CN-122001361-A - Multiplexing system of single-ended-to-differential signal driver and detector readout chip

CN122001361ACN 122001361 ACN122001361 ACN 122001361ACN-122001361-A

Abstract

The invention provides a multiplexing system of a single-ended differential signal driver and a detector reading chip, and belongs to the technical field of active electrical nonlinear devices. The system comprises a multi-channel capacitive transimpedance amplifier, a corresponding switched capacitor sampling and holding circuit in a ping-pong mode, a multiplexer, a single-ended to differential signal driver and an ADC. The capacitive transimpedance amplifier of the selected channel receives the X-ray signal and voltage of the photoelectric sensor response The signal charge is stored on a group of holding capacitors through a corresponding switched capacitor sampling hold circuit, the signal charge is connected to the input end of a single-ended to differential signal driver through a multiplexer, the ADC quantitatively outputs, and the single-ended to differential signal driver is of a switched capacitor type circuit structure. The invention saves the voltage for driving CTIA output during multi-channel switching And the required unit gain voltage Buffer removes extra noise introduced by Buffer, and reduces power consumption and layout area.

Inventors

XU JINGE
CHEN GUANGYI
LIU DAHE
SHI XUEYOU
LI KEZHI

Assignees

北京安酷影芯科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260115

Claims (10)

1. A multiplexing system of single-ended differential signal driver is characterized in that the multiplexing system comprises a multi-channel capacitance transresistance amplifier, a ping-pong type switch capacitance sampling hold circuit corresponding to the capacitance transresistance amplifier, a multiplexer MUX, a single-ended differential signal driver and an ADC, Wherein the capacitive transimpedance amplifier of the selected channel receives the X-ray signal responded by the photosensor and generates a corresponding voltage Voltage, voltage Storing corresponding signal charges on one of two groups of holding capacitances of the switched capacitor sample hold circuit in the ping-pong form through the corresponding switched capacitor sample hold circuit in the ping-pong form, Through the multiplexer MUX, two groups of holding capacitors of the ping-pong type switched capacitor sampling and holding circuit are connected to the input end and the output end of the single-ended to differential signal driver in a bridging way, through the reverse connection, the operational amplifier driving charges of the single-ended to differential signal driver are redistributed on one group of holding capacitors to generate positive and negative output voltages of the single-ended to differential signal driver, the positive and negative output voltages are sampled by the positive input end and the negative input end of the ADC, the quantized output is carried out through the ADC, The single-ended to differential signal driver is of a switched capacitor type circuit structure.
2. The multiplexing system as described in claim 1, wherein each of the two sets of holding capacitances CH is split into two capacitances C p and C n of equal and opposite polarities, After the end of the integral phase of the capacitor transimpedance amplifier and the tracking and holding of a group of holding capacitors are finished, the connection with the output end of the capacitor transimpedance amplifier is disconnected, the single-ended suspension holds charges, The other group of holding capacitors are connected with the capacitor transimpedance amplifier to track and hold the next row of signals.
3. The multiplexing system of claim 1 or 2, wherein the output voltage swing of the capacitive transimpedance amplifier is At the end of the integral phase of the capacitive transimpedance amplifier, a sampling switch SMP of the switched capacitor sampling hold circuit in a ping-pong form is disconnected, the single ends of the holding capacitors C p and C n are suspended, and the other end is connected with The signal charges are stored in the holding capacitors C p and C n , and the absolute voltage difference between the two ends of the holding capacitors C p and C n is 。
4. A multiplexing system in accordance with claim 3 wherein the holding capacitor C p of the ping-pong switched capacitor sample-and-hold circuit is connected on one side to the positive input of the fully differential operational amplifier of the single-ended to differential signal driver and on the other side from the reset voltage to which the ping-pong switched capacitor sample-and-hold circuit is connected Switching to the negative output of the fully differential operational amplifier , The suspension end of one side of the holding capacitor C n is connected with the positive output end of the fully-differential operational amplifier of the single-ended to differential signal driver The other side is connected with the reset voltage Switching to negative output The positive input end and the negative input end of the fully differential operational amplifier of the single-ended to differential signal driver have the same voltage and are And if so, the voltage of the output end of the operational amplifier is as follows: Wherein, the The voltage difference representing the left plate voltage minus the right plate voltage of holding capacitance C p , The voltage difference of the right plate voltage minus the left plate voltage of the holding capacitor C n is shown.
5. The multiplexing system of claim 4, wherein the positive output of the fully differential operational amplifier of the single-ended to differential signal driver is represented by the following equation And a negative output terminal And (3) subtracting: Wherein, the Two groups of common mode voltages And Independent of each other.
6. The multiplexing system of claim 2, wherein the single-ended to differential signal driver comprises a fully differential operational amplifier, a first capacitor connected in parallel with a positive input and a positive output of the fully differential operational amplifier, and a second capacitor connected in parallel with a negative input and a negative output of the fully differential operational amplifier.
7. The multiplexing system of claim 6, wherein the first capacitor has a switch HD 1 and a switch HDd 1 connected in series across the first capacitor, respectively, and a switch RST 1 connected in parallel across the first capacitor; The two ends of the second capacitor are respectively connected with a switch HD 2 and a switch HDd 2 in series, and the second capacitor is connected with a switch RST 2 in parallel.
8. The multiplexing system of claim 7, wherein the holding capacitances C p and C n are each split into corresponding 1/2 capacitances and the upper and lower plates are connected, the upper and lower plates have different voltage coefficients and parasitic capacitances, positive and negative offsets make the voltage coefficient zero, After the single-ended to differential signal driver is reset, the switch RST 1 or the switch RST 2 is opened, the corresponding switch HDd 1 or the switch HD 2 is closed, and the free ends of the holding capacitors C p and C n of the switched capacitor sample hold circuit in the ping-pong form are respectively connected to the positive input end and the positive output end of the fully differential operational amplifier of the single-ended to differential signal driver The other ends are all connected with Negative input and negative output of a fully differential operational amplifier respectively switched to the single-ended to differential signal driver And based on the operation of the inverse connection of the capacitor, completing the common mode operation of the signals.
9. The multiplexing system of claim 6, wherein the first capacitor and the second capacitor correspond to multiplexing the holding capacitors C p and C n , respectively.
10. A multi-channel detector readout chip, characterized in that it comprises a multiplexing system according to any of claims 1-9.

Description

Multiplexing system of single-ended-to-differential signal driver and detector readout chip Technical Field The invention relates to the technical field of active electrical nonlinear devices, in particular to a multiplexing system of a single-ended differential signal driver and a detector reading chip. Background The core of the single-ended-to-differential circuit is to convert one single-ended signal into two differential signals with opposite phases. The differential signal has better common-mode interference resistance, and is suitable for high-fidelity audio signals, analog-to-digital converter (Analog to Digital Converter, ADC) driving and other applications. Most modern high-performance ADCs use differential inputs to suppress common mode noise and interference, and due to the balanced signal processing mode, the dynamic range can be improved by 2 times by using the method, so that the overall performance of the system is improved. The X-ray detector system is a device for converting X-ray energy into a digitized signal image, and plays a great role in the fields of medical diagnosis, safety inspection, nondestructive inspection, industrial flaw detection, and the like. The Read-Out Integrated Circuit (ROIC) is one of the core components of the X-ray detector, and the capacitive transimpedance amplifier (CAPACITIVE TRANSIMPEDANCE AMPLIFIER, CTIA) module meets the special performance requirements of the X-ray Read-out circuit, can integrate and amplify weak charge signals, convert the weak charge signals into detectable voltage signals, and is widely used as a charge sensitive amplifier at the analog front end of the Read-out circuit. In the related art, the circuit structure of the single-ended to differential driver is shown in fig. 1, the resistance of the circuit is about kΩ level, and a unit gain buffer with large current driving capability is added to the output end of the CTIA for load matching during multi-channel switching, so that the overall power consumption and noise are difficult to reduce. Disclosure of Invention The embodiment of the invention aims to provide a multiplexing system of a single-ended-to-differential signal driver and a detector readout chip, and aims to solve the problem that when a plurality of channels are switched, a unit gain buffer with large current driving capability is added at a CTIA output end for load matching, and overall power consumption and noise are difficult to reduce. In order to achieve the above objective, an embodiment of the present invention provides a multiplexing system of a single-ended to differential signal driver, which includes a multi-channel capacitive transimpedance amplifier, a switched capacitor sample-and-hold circuit in a ping-pong form corresponding to the capacitive transimpedance amplifier, a multiplexer MUX, a single-ended to differential signal driver, and an ADC. Wherein the capacitive transimpedance amplifier of the selected channel receives the X-ray signal responded by the photosensor and generates a corresponding voltageVoltage, voltageAnd through the multiplexer MUX, the two groups of holding capacitors of the switched capacitor sampling and holding circuit in the ping-pong form are connected to the input end and the output end of the single-ended differential signal driver in a bridging way, and through the inverse connection, the operational amplifier driving charges of the single-ended differential signal driver are redistributed on the groups of holding capacitors to generate positive and negative output voltages of the single-ended differential signal driver, sampled by the positive input end and the negative input end of the ADC, and quantized output is performed through the ADC. The single-ended to differential signal driver is of a switched capacitor type circuit structure. In an alternative embodiment, each of the two sets of holding capacitances CH is split into two capacitances C p and C n having equal capacitance values and opposite polarities. And after the end of the integral phase of the capacitor transimpedance amplifier, one group of holding capacitors are disconnected from the output end of the capacitor transimpedance amplifier after tracking and holding are finished, and the single end of the holding capacitors is suspended to hold charges, and the other group of holding capacitors are connected with the capacitor transimpedance amplifier to track and hold the next row of signals. In an alternative embodiment, the output voltage swing of the capacitive transimpedance amplifier isAt the end of the integral phase of the capacitive transimpedance amplifier, a sampling switch SMP of the switched capacitor sampling hold circuit in a ping-pong form is disconnected, the single ends of the holding capacitors C p and C n are suspended, and the other end is connected withThe signal charges are stored in the holding capacitors C p and C n, and the absolute voltage difference between the two ends of the holding ca