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CN-122001364-A - Front-stage circuit of high-speed low-noise charge pump phase-locked loop

CN122001364ACN 122001364 ACN122001364 ACN 122001364ACN-122001364-A

Abstract

The invention discloses a high-speed low-noise charge pump phase-locked loop pre-stage circuit, which belongs to the field of integrated circuit radio frequency and comprises a high-speed phase frequency detector and a high-speed charge pump, wherein the high-speed phase frequency detector carries out phase frequency detection on a reference signal f REF and a feedback signal f VCO , and the high-speed charge pump carries out charge and discharge according to UP and DN signals output by the high-speed phase frequency detector. The invention can realize the frequency and phase discrimination and low mismatch charge and discharge work under the highest frequency 6.4GHz input signal, and simultaneously has low noise performance. The high-speed low-noise high-speed phase frequency detector provided by the invention can realize the phase frequency detection and low-mismatch charge and discharge work under the highest frequency 6.4GHz input signal based on the mature SiGe process platform, and simultaneously has low noise performance.

Inventors

  • QIN ZHANMING
  • FAN HAIYU
  • JIANG YINGDAN
  • SUN WENJUN
  • WANG BAIKANG
  • YANG JUNHAO
  • SHEN JIAN

Assignees

  • 中国电子科技集团公司第五十八研究所

Dates

Publication Date
20260508
Application Date
20260122

Claims (6)

  1. 1.A high-speed low-noise charge pump phase-locked loop pre-stage circuit, comprising: The high-speed phase frequency discriminator performs phase frequency discrimination on the reference signal f REF and the feedback signal f VCO ; And the high-speed charge pump charges and discharges according to the UP and DN signals output by the high-speed phase frequency detector.
  2. 2. The high-speed low-noise charge pump phase-locked loop pre-stage circuit of claim 1, wherein the high-speed phase-frequency detector comprises a first CML structure D flip-flop and a second CML structure D flip-flop with core reset, a CML structure and gate logic, a first output buffer and a second output buffer, resistors R 1 and R 2 , and a transistor Q 0 ; The positive input end D of the first CML structure D trigger and the positive input end D of the second CML structure D trigger are both connected with a power supply voltage V CC , the reverse input end DN is both connected with V CC through a resistor R 1 and is simultaneously connected with the collector electrode of a triode Q 0 ; The positive input end CLK of the first CML structure D trigger is connected with the reference signal f REF , the negative input end CLKn is connected with the reference signal f REFn , the positive input end CLK of the second CML structure D trigger is connected with the feedback signal f VCO , and the negative input end CLKn is connected with the feedback signal f VCOn ; The forward output end Q of the first CML structure D trigger is simultaneously connected with the forward input end of the first output buffer and the input end A 1 of the CML structure AND gate logic, the reverse output end QN of the first CML structure D trigger is connected with the reverse input end of the first output buffer, the forward output end Q of the second CML structure D trigger is simultaneously connected with the forward input end of the second output buffer and the input end A 2 of the CML structure AND gate logic, the reverse output end QN of the second CML structure D trigger is connected with the reverse input end of the second output buffer, the forward output ends of the first output buffer and the second output buffer are respectively UP and DN, the reverse output ends are respectively UPn and DNn, the base electrode of the triode Q 0 is connected with the bias voltage V REF , and the emitter electrode is connected to the ground through a resistor R 2 .
  3. 3. The high-speed low-noise charge pump phase-locked loop pre-stage circuit according to claim 2, wherein the first CML structure D flip-flop and the second CML structure D flip-flop have the same structure and respectively comprise a triode Q 33 ~Q 48 and a resistor R 29 ~R 34 ; The base of transistor Q 33 and the base of Q 36 are simultaneously connected to the forward clock input CLK, the base of transistor Q 34 and the base of Q 35 are simultaneously connected to the reverse clock output CLKn, the emitter of transistor Q 33 , the emitter of Q 34 and the emitter of Q 37 are simultaneously connected to the collector of Q 47 , the emitter of triode Q 35 , The emitter of Q 36 and the emitter of Q 38 are simultaneously connected to the collector of Q 48 , the collector of triode Q 33 is connected to the emitter of Q 39 and the emitter of Q 40 , the collector of triode Q 34 is connected to the emitter of Q 41 and the emitter of Q 42 , the collector of triode Q 35 is connected to the emitter of Q 43 and the emitter of Q 44 , the collector of triode Q 36 is connected to the emitter of Q 45 and the emitter of Q 46 , the base of triode Q 39 and the base of Q 40 are respectively connected to data terminals D and Dn, the collector of triode Q 39 is connected to the collector of power supply voltage V CC ,Q 39 through resistor R 29 and is simultaneously connected to the collector of Q 41 , The base of Q 42 and the base of Q 44 , the collector of Q 40 is connected to the collector of the power supply voltage V CC ,Q 40 through a resistor R 30 and simultaneously connected to the collector of Q 42 and the collector of Q 37 , The base of Q 41 and the base of Q 43 , the collector of the transistor Q 43 is connected to the collector of the power voltage V CC ,Q 43 through a resistor R 31 and is connected to the collector of Q 45 , The base of Q 46 and the inverted clock output terminal Qn, the collector of the transistor Q 44 is connected to the collector of the power supply voltage V CC ,Q 44 through a resistor R 32 and is connected to the collector of Q 46 , A base electrode of Q 45 , The collector of Q 38 and the positive clock output end Q, the base of triode Q 37 and the base of Q 38 are respectively connected with the reset end RST, the base of triode Q 47 and the base of Q 48 are respectively connected with bias voltage V REF , and the emitter of triode Q 47 and the emitter of Q 48 are respectively connected to ground through resistors R 33 and R 44 .
  4. 4. The high-speed low-noise charge pump phase-locked loop pre-stage circuit according to claim 2, wherein said CML structure and gate logic comprises transistor Q 49 ~Q 54 , resistor R 35 ~R 54 ; The base of the triode Q 49 and the base of the triode Q 50 are respectively connected with a forward input end A and a reverse input end An, the collector of the triode Q 49 is connected with the collector of the power supply voltage V CC ,Q 49 through a resistor R 35 and is connected with the reverse output end ZN, the collector of the triode Q 50 is connected with the collector of the power supply voltage V CC ,Q 50 through a resistor R 36 and is connected with the collector of the Q 52 , The collector and the forward output end Z of Q 54 , the base electrode of the triode Q 51 and the base electrode of the Q 52 are respectively connected with the forward input end B and the reverse input end Bn, the emitter electrode of the triode Q 51 and the emitter electrode of the Q 52 are simultaneously connected with the collector electrode of the Q 53 , the base electrode of the triode Q 53 and the base electrode of the Q 54 are simultaneously connected with the bias voltage V REF , and the emitter electrode of the triode Q 53 and the emitter electrode of the Q 54 are respectively connected with the ground in series through resistors R 37 and R 38 .
  5. 5. The high-speed low-noise charge pump phase-locked loop pre-stage circuit according to claim 4, wherein said first output buffer and said second output buffer have the same structure and respectively comprise a triode Q 55 ~Q 58 and a resistor R 39 ~R 40 ; The collector of the triode Q 55 and the collector of the triode Q 56 are both connected to a power supply voltage V CC , the base of the triode Q 55 and the base of the triode Q 56 are respectively connected to a forward input end A and a reverse input end AN, the emitter of the triode Q 55 is connected to the collector of the triode Q 57 and a forward output end OUT, the emitter of the triode Q 56 is connected to the collector of the triode Q 58 and a reverse output end OUTn, and the emitter of the triode Q 57 and the emitter of the triode Q 58 are respectively connected to ground through resistors R 39 and R 40 .
  6. 6. The high-speed low-noise charge pump phase-locked loop pre-stage circuit according to claim 1, wherein the high-speed charge pump comprises a triode Q 1 ~Q 32 , a resistor R 1 ~R 28 , a PMOS tube M 1 ~M 9 and an NMOS tube M 10 ~M 15 ; The source end of the PMOS tube M 1 ~M 3 is connected to the power supply voltage V CC through a resistor R 1 ~R 3 , the source end of the PMOS tube M 4 ~M 6 is connected to the drain end of the M 7 ~M 9 through a resistor R 4 ~R 6 , the source ends of the M 7 ~M 9 are both connected to the gate end of the power supply voltage V CC ;M 1 ~M 6 and the drain end of the M 1 together and connected to a current source I, the gate ends of the M 7 ~M 9 are respectively connected to a control signal up <0>, up <1>, UP <2>, the drain terminal of M 4 ~M 6 is connected to output terminal CPout, the emitter of triode Q 1 ~Q 6 is respectively connected to ground through resistor R 17 ~R 22 , the base of Q 1 is connected with self-collector, and at the same time the base of Q 2 is connected with base of Q 3 , the base of Q 4 is connected with self-collector, and at the same time the base of Q 5 is connected with base of Q 6 , the collector of triode Q 2 is connected with emitter of Q 7 and emitter of Q 8 , the collector of triode Q 3 is connected with emitter of Q 9 and emitter of Q 10 , and the base of triode Q 7 ~Q 10 is respectively connected with output UP of high-speed phase frequency detector, UPn (UPn), DN and DNn, the base of transistor Q 11 ~Q 14 being connected to the collector of Q 7 ~Q 10 , the collector of transistor Q 1 、Q 7 、Q 8 、Q 9 、Q 10 being connected to the drain of PMOS transistor M 2 by resistor R 7 ~R 11 , the collector of transistor Q 4 、Q 11 、Q 12 、Q 13 、Q 14 being connected to the drain of PMOS transistor M 3 by resistor R 12 ~R 16 , the collectors of transistor Q 11 being connected to the bases of Q 16 、Q 20 and Q 24 , the collectors of transistor Q 12 being connected to the bases of Q 15 、Q 19 and Q 23 , the collectors of transistor Q 13 being connected to the bases of Q 17 、Q 21 and Q 25 , the collectors of transistor Q 14 being connected to the bases of Q 18 、Q 22 and Q 18 、Q 22 , the emitter of transistor Q 18 、Q 22 and the emitter of Q 18 、Q 22 being connected to the drain of NMOS transistor M 18 、Q 22 by resistor R 18 、Q 22 , the emitter of Q 18 、Q 22 and the emitter of Q 18 、Q 22 being connected to the drain of NMOS transistor M 18 、Q 22 by resistor R 18 、Q 22 14 The drain terminal of the NMOS transistor M 15 is commonly connected with the emitter of the triode Q 25 and the emitter of the triode Q 26 through a resistor R 28 , the source terminal of the NMOS transistor M 10 ~M 15 is grounded, the gate terminal control terminals dn <0> of the NMOS transistors M 10 and M 11 , the gate terminal control terminals dn <1> of the NMOS transistors M 12 and M 13 , the gate terminal control terminals dn <2> of the NMOS transistors M 14 and M 15 , the collectors of the triodes Q 16 、Q 18 、Q 20 、Q 22 、Q 24 and Q 26 are connected with the output terminal CPout, the collectors of the triodes Q 15 、Q 17 、Q 19 、Q 21 、Q 23 and Q 25 are respectively connected with the emitter of the triode Q 27 ~Q 32 , the base and the collector of the triode Q 27 ~Q 32 are connected with the power supply voltage V CC .

Description

Front-stage circuit of high-speed low-noise charge pump phase-locked loop Technical Field The invention relates to the technical field of integrated circuit radio frequency, in particular to a high-speed low-noise charge pump phase-locked loop pre-stage circuit. Background With the continued advancement of modern integrated circuit technology, the need for high-speed, low-noise frequency doubling systems has increased. The phase-locked loop structure is widely used in clock frequency multipliers, and a high-speed phase frequency detector and a high-speed charge pump are core modules of the phase-locked loop. The traditional high-speed phase frequency detector is designed by a digital circuit, and the maximum working frequency is about 200 MHz. When the output frequency of the voltage-controlled oscillator is required to be higher and the frequency division ratio is smaller, the traditional high-speed phase frequency detector cannot process the output frequency, so that the overall performance of the phase-locked loop is affected. The switching tube and UP/DN current of the traditional high-speed charge pump work in the same branch, when the working frequency is higher, the output pulse of the phase frequency detector is very narrow and the switching is fast, a tiny mismatch can inject net charge into the loop filter in each period, and a periodic ripple wave is generated to cause the phase-locked loop to generate larger reference strays. In addition, non-ideal factors such as clock feedthrough, charge injection, and charge sharing exist to affect overall performance. In view of the foregoing, it is desirable to provide a high-speed low-noise charge pump pll front-end circuit. Disclosure of Invention The invention aims to provide a high-speed low-noise charge pump phase-locked loop pre-stage circuit so as to realize frequency and phase discrimination and low-mismatch charge and discharge work under the highest frequency 6.4G input signal and simultaneously consider low-noise performance. In order to solve the technical problems, the present invention provides a high-speed low-noise charge pump phase-locked loop pre-stage circuit, comprising: The high-speed phase frequency discriminator performs phase frequency discrimination on the reference signal f REF and the feedback signal f VCO; And the high-speed charge pump charges and discharges according to the UP and DN signals output by the high-speed phase frequency detector. In one embodiment, the high-speed phase frequency detector comprises a first CML structure D trigger and a second CML structure D trigger with a core reset, a CML structure AND gate logic, a first output buffer and a second output buffer, resistors R 1 and R 2 and a triode Q 0; The positive input end D of the first CML structure D trigger and the positive input end D of the second CML structure D trigger are both connected with a power supply voltage V CC, the reverse input end DN is both connected with V CC through a resistor R 1 and is simultaneously connected with the collector electrode of a triode Q 0; The positive input end CLK of the first CML structure D trigger is connected with the reference signal f REF, the negative input end CLKn is connected with the reference signal f REFn, the positive input end CLK of the second CML structure D trigger is connected with the feedback signal f VCO, and the negative input end CLKn is connected with the feedback signal f VCOn; The forward output end Q of the first CML structure D trigger is simultaneously connected with the forward input end of the first output buffer and the input end A 1 of the CML structure AND gate logic, the reverse output end QN of the first CML structure D trigger is connected with the reverse input end of the first output buffer, the forward output end Q of the second CML structure D trigger is simultaneously connected with the forward input end of the second output buffer and the input end A 2 of the CML structure AND gate logic, the reverse output end QN of the second CML structure D trigger is connected with the reverse input end of the second output buffer, the forward output ends of the first output buffer and the second output buffer are respectively UP and DN, the reverse output ends are respectively UPn and DNn, the base electrode of the triode Q 0 is connected with the bias voltage V REF, and the emitter electrode is connected to the ground through a resistor R 2. In one embodiment, the first CML structure D flip-flop and the second CML structure D flip-flop have the same structure and respectively include a transistor Q 33~Q48 and a resistor R 29~R34; The base of transistor Q 33 and the base of Q 36 are simultaneously connected to the forward clock input CLK, the base of transistor Q 34 and the base of Q 35 are simultaneously connected to the reverse clock output CLKn, the emitter of transistor Q 33, the emitter of Q 34 and the emitter of Q 37 are simultaneously connected to the collector of Q 47, the emitte