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CN-122001365-A - Frequency modulation synchronizer for clock domain crossing

CN122001365ACN 122001365 ACN122001365 ACN 122001365ACN-122001365-A

Abstract

The present disclosure relates to frequency-modulated synchronizers for clock domain crossing. A synchronizer with flip-flops having a reduced number of serially coupled flip-flops that receive data in a first clock domain as an input and provide data in a second clock domain as an output. The second clock signal is at a variable frequency that is adjusted to the target frequency by a division factor. The flip-flop is clocked by the clock signal which sub-samples the second clock signal by a factor k 1. The sub-sampling clock signal is generated by a frequency divider that propagates one pulse of the signal every k1 clock pulses while maintaining edge alignment.

Inventors

  • LACAN JEROME
  • C. Eva

Assignees

  • 意法半导体国际公司

Dates

Publication Date
20260508
Application Date
20251103
Priority Date
20241104

Claims (20)

  1. 1. An apparatus, comprising: a series-coupled set of first flip-flops receiving first data in a first clock domain based on a first clock signal, an A clock adjustment circuit comprising: an input configured to receive a second clock signal asynchronous to the first clock signal; an adjusting circuit configured to generate an adjusted clock signal having a period greater than a period of the second clock signal, and An output coupled to the clock input of each flip-flop and configured to provide an adjusted clock signal to the clock input of each first flip-flop, wherein the set of first flip-flops is configured to output the first data in a second clock domain that is asynchronous to the first clock domain and based on the second clock signal.
  2. 2. The apparatus of claim 1, wherein the adjustment circuit comprises a sub-sampler configured to sub-sample the second clock signal by a sub-sampling factor, the sub-sampling factor being an integer greater than or equal to 2, the sub-sampler receiving the second clock signal as an input signal and outputting the adjusted clock signal.
  3. 3. The apparatus of claim 2, wherein the adjustment circuit comprises a clock divider upstream of the sub-sampler, the clock divider configured to adjust the second clock signal by a division factor corresponding to an integer greater than or equal to 2.
  4. 4. The apparatus of claim 3, wherein the sub-sampler comprises means for adapting the sub-sampling factor to an adjustment of the frequency of the second clock signal by the division factor.
  5. 5. The apparatus of claim 2, wherein the sub-sampler comprises a counter configured to count pulses of a second clock signal and a clock gating unit coupled to the counter.
  6. 6. The apparatus of claim 1, wherein the set of flip-flops comprises only two flip-flops in series.
  7. 7. The apparatus of claim 1, wherein the sub-sampling factor k is fixed at a factor k2 selected from factors of N sync -1 when the mean time to failure formula relates the theoretical number of flip-flops N sync to the first frequency of the first clock signal and the second frequency of the second clock signal.
  8. 8. The apparatus of claim 1, wherein the adjustment circuit comprises a clock divider configured to generate the adjusted clock signal by dividing the second clock signal by a division factor, the division factor corresponding to an integer greater than or equal to 2.
  9. 9. The apparatus of claim 1, comprising a set of second flip-flops coupled in series and receiving the second data in a third clock domain based on a third clock signal, and each second flip-flop having a clock input coupled to receive the adjusted clock signal from the clock adjustment circuit, wherein the clock adjustment causes the second flip-flop to output the second data in the second clock domain, the third clock domain being asynchronous with the second clock domain.
  10. 10. A method for synchronizing between a first clock domain clocked by a first clock signal and a second clock domain asynchronous to the first clock domain and clocked by a second clock signal, the method comprising: acquiring at least one clock division factor or clock sub-sampling factor; adjusting the variable frequency of the second clock signal to a target frequency based on the clock division factor to provide an adjusted clock signal clocking the flip-flop, and With the adjusted clock signal, flip-flops in series in a synchronization unit that receives data in a first clock domain as input and provides data in a second clock domain as output are controlled.
  11. 11. The method of claim 10, wherein adjusting the variable frequency comprises dividing the second clock signal by a divider to generate an adjusted clock signal.
  12. 12. The method of claim 10, wherein adjusting the variable frequency comprises sub-sampling the second clock signal with a sub-sampler to generate an adjusted clock signal.
  13. 13. The method of claim 10, wherein adjusting the variable frequency comprises dividing the frequency of the second clock signal with a divider and sub-sampling the output of the divider with a sub-sampler to generate the adjusted clock signal.
  14. 14. A method, comprising: receiving first input data in a first clock domain based on a first clock signal using a set of first flip-flops coupled in series; receiving a second clock signal asynchronous to the first clock signal with a clock adjustment circuit; Generating an adjusted clock signal having a period greater than the period of the second clock signal using the clock adjustment circuit, and Providing the adjusted clock signal to the clock input of each first flip-flop, and The first input data is output from the set of first flip-flops in a second clock domain based on a second clock signal.
  15. 15. The method of claim 14, wherein generating the adjusted clock signal comprises dividing a second clock signal with a divider of the frequency adjustment circuit.
  16. 16. The method of claim 14, wherein generating the variable frequency comprises sub-sampling a second clock signal with a sub-sampler of a clock adjustment circuit.
  17. 17. The method of claim 16, wherein the sub-sampler comprises a counter configured to count pulses of a second clock signal and a clock gating unit coupled to the counter.
  18. 18. The method of claim 14, wherein the set of first flip-flops comprises only two first flip-flops in series.
  19. 19. The method of claim 14, wherein generating the variable frequency comprises generating a divided clock signal by dividing the frequency of the second clock signal with a divider and sub-sampling an output of the divider with a sub-sampler.
  20. 20. The method of claim 11, further comprising: Receiving second data in a third clock domain based on a third clock signal with a set of second flip-flops coupled in series; providing the adjusted clock signal to the clock input of each second flip-flop, and The second data is output from the set of second flip-flops in a second clock domain, the second clock domain being asynchronous to the first clock domain.

Description

Frequency modulation synchronizer for clock domain crossing Technical Field Embodiments and implementations relate to the field of synchronizing data in a system having an asynchronous clock domain. Background Digital systems are typically composed of several digital subsystems. When the digital subsystems operate synchronously with the same clock, there is no need to synchronize signals flowing between the digital subsystems. On the other hand, if the digital subsystems are asynchronous, i.e. operate with clocks that are asynchronous at least in phase, the signals that circulate between the digital subsystems must be synchronized. For example, a computer system may operate at a given frequency, while a processor may operate at another frequency. Interface circuits that enable data to be transferred from one clock domain to another are referred to as synchronization units or "synchronizers. Fig. 1 illustrates a synchronizer with a flip-flop 100 for synchronizing a data signal sig_1 according to the prior art. Flip-flop a 105 operates in original clock domain a 107. A set of flip-flops B operate in the target clock domain B114. In a known manner, a flip-flop is a logic circuit that uses operators between its inputs and maintains the value of its one or more outputs (estimated at the clock edge) during a clock cycle. Clock domain a 107 and clock domain B114 are asynchronous clock domains. The flip-flop a 105 receives the input signal sig_1 at its data input "d" and is clocked (timed) at a first clock frequency f A by a first clock signal clk_a at its clock input. Fig. 1 illustrates a set of four flip-flops B1, B2, B3, 112, and B4, 110, B2, B3, B113 operating in series or "cascade" (the output "q" of the previous flip-flop providing the input "d" of the next flip-flop). Other numbers of triggers are contemplated. In particular, synchronizers having two flip-flops B are well known. The input signal sig_1 is transmitted to the output "q" of the flip-flop a 105 by the action of the first clock signal clk_a. The flip-flops in group B are clocked by the second clock signal clk_b at the second clock frequency f B and the output signal at the output "q" of flip-flop a 105 is transmitted in series through each flip-flop in group B until a final output "q" at the output node 120. If one clock source (e.g., f B) has the maximum operating frequency (f Bmax), but the frequency may be variable in case the user can adjust the domain frequency by means of a clock divider integrated in the clock source. Fig. 2 illustrates a timing diagram 200 of signals of the synchronizer 100. The signals a q 205 at the output of flip-flop a 105 (i.e. at the input of the target clock domain B114), the clock signal clk_b207 of the target clock domain B114, the signal b1_q210 at the output of the first flip-flop B1 110, the signal b2_q211 at the output of the next flip-flop B2 111, the signal b3_q212 at the output of the further next flip-flop B3 112 and the signal b4_q213 at the output of the last flip-flop B4 113 are shown. Here, the signal b4_q corresponds to the OUTPUT signal OUTPUT (OUTPUT) 120. Each output signal bi_q of intermediate flip-flop Bi corresponds to input signal B (i+1) _d of subsequent intermediate flip-flop B (i+1). There is a possibility that during sampling of the signal a q by the flip-flop B1 110 in the target clock domain 114, the output b1_q of the flip-flop B1 may enter a metastable state. This possibility (which decreases over time) is symbolically illustrated by the shading after each edge. The subsequent flip-flop B2 is less likely to happen the same way (symbolically indicated by shading), and so on. These metastable risks depend on the parameters of the flip-flop and the target frequency f B of the clock clk_b. These four flip-flops are connected in series, reducing the risk of metastability at the output 120 at the cost of offset sampling by the number of clock cycles corresponding to the number of additional flip-flops (e.g., relative to a synchronizer with two flip-flops). The number of flip-flops B to be used N sync is generally determined by the following equation: wherein the decision time t is equal to MTBF is mean time to failure. T r (the resolution time of the flip-flops), T W (the metastable window), N (the total number of flip-flops in the synchronizer or synchronization system), T setup (the flip-flop setup duration), T cp→q (the delay time CP (clock pulse) at the Q (output) of the flip-flop), T uncertainty (the constant) are fixed parameters, related to the selected flip-flop and/or circuit design. The larger number of flip-flops N sync is detrimental to the compactness of the synchronizer 100 as well as to its power consumption. It also delays the transition of the input signal sig_1 in the target clock domain. To contain this number, it is necessary to improve the performance of the flip-flop, but this is costly. Furthermore, seeking enhanced performance of clock domain B114 is typically accompan