CN-122001367-A - Low-noise high-frequency voltage-controlled oscillator design

CN122001367ACN 122001367 ACN122001367 ACN 122001367ACN-122001367-A

Abstract

The specification discloses a low-noise high-frequency voltage-controlled oscillator design, and relates to the field of oscillator design. The design method is mainly designed for establishing a phase domain linear model of a phase-locked loop, deducing a noise transfer function of each partial circuit, obtaining phase noise performance analysis of each partial circuit through simulation, adopting an NMOS cross coupling structure of a 9-bit capacitor array LC voltage-controlled oscillator, enabling parasitic capacitance to be smaller, obtaining a larger frequency modulation range, designing parameter values of main elements in a charge pump of a phase discriminator, reducing influence of noise such as a power supply, and improving phase noise performance of the voltage-controlled oscillator. The problem of the output amplitude of current oscillator is smaller and smaller, leads to phase noise performance decline is solved.

Inventors

WANG WEIHUA
CUI WEI
ZHENG WENQIANG

Assignees

北京无线电计量测试研究所

Dates

Publication Date: 20260508
Application Date: 20251223

Claims (4)

1. The design is characterized by comprising a phase-locked loop circuit design, a voltage-controlled oscillator circuit design, a phase discriminator and a charge pump design; The fractional part of the frequency division ratio N.f set by the phase-locked loop circuit firstly carries out noise shaping through a sigma delta modulator, quantization noise is pushed to the high end of a frequency spectrum, the output of the sigma delta modulator is added with the integer part of the set frequency division ratio, the obtained result is used for controlling the frequency division ratio of the frequency divider, and an output frequency signal which is N.f times of the frequency of a reference signal is obtained at the output of the voltage-controlled oscillator; the voltage-controlled oscillator circuit adopts an NMOS cross-coupling structure of a 9-bit capacitor array LC voltage-controlled oscillator; The charge pump adopts a source electrode switch structure; the current mirror in the charge pump increases the output impedance of the current source for the cascode structure.
2. The design of claim 1, wherein the ΣΔ modulator has a multi-stage structure and a single-stage structure.
3. The design of claim 1, wherein the ΣΔ modulator of the MASH architecture is a multi-stage architecture.
4. The design of claim 1, wherein the voltage controlled oscillator circuit is an NMOS cross-coupled structure, is less limited by supply voltage, has less parasitic capacitance, and achieves a greater frequency modulation range.

Description

Low-noise high-frequency voltage-controlled oscillator design Technical Field The present document relates to the field of oscillator design, and in particular, to a low noise high frequency voltage controlled oscillator design. Background The oscillator serves as a signal source in the electronic device system to provide a stable clock signal. Along with the expansion of the communication frequency range, the requirements of error rate in the communication standard are ensured, the indexes of frequency accuracy and frequency stability are improved, along with the development of the CMOS processing technology, the thickness of a transistor gate oxide layer is thinner and thinner, and the bias voltage which can be provided is smaller and smaller, so that the output amplitude of an oscillator is smaller and smaller, and the phase noise performance is further reduced. Disclosure of Invention The specification provides a low-noise high-frequency voltage-controlled oscillator design, which is used for solving the problem that the output amplitude of the current oscillator is smaller and smaller, so that the performance of phase noise is reduced. In a first aspect, the present specification provides a low noise high frequency voltage controlled oscillator design comprising a phase locked loop circuit design, a voltage controlled oscillator circuit design, and a phase detector and charge pump design; The fractional part of the frequency division ratio N.f set by the phase-locked loop circuit firstly carries out noise shaping through a sigma delta modulator, quantization noise is pushed to the high end of a frequency spectrum, the output of the sigma delta modulator is added with the integer part of the set frequency division ratio, the obtained result is used for controlling the frequency division ratio of the frequency divider, and an output frequency signal which is N.f times of the frequency of a reference signal is obtained at the output of the voltage-controlled oscillator; the voltage-controlled oscillator circuit adopts an NMOS cross-coupling structure of a 9-bit capacitor array LC voltage-controlled oscillator; The charge pump adopts a source electrode switch structure; the current mirror in the charge pump increases the output impedance of the current source for the cascode structure. The beneficial effects of the invention are as follows: the specification provides a frequency synthesizer design employing a fractional-N phase-locked loop, and relates to the field of oscillator design. According to the design method, the phase noise performance of each part of circuit is obtained through deduction of the noise transfer function of each part of circuit and simulation, according to analysis of noise and frequency range, the parasitic capacitance is smaller due to the NMOS cross coupling structure of the 9-bit capacitor array LC voltage-controlled oscillator, a larger frequency modulation range can be obtained, parameter values of main elements in the charge pump are designed, influence of noise such as a power supply is reduced, and the phase noise performance of the voltage-controlled oscillator is improved. The problem of the output amplitude of current oscillator is smaller and smaller, leads to phase noise performance decline is solved. Drawings The accompanying drawings, which are included to provide a further understanding of the specification, illustrate and explain the exemplary embodiments of the present specification and their description, are not intended to limit the specification unduly. In the drawings: Fig. 1 is a schematic diagram of a phase locked loop frequency synthesizer according to an embodiment of the present disclosure; FIG. 2 is a schematic illustration of the structure of one MASH 1-1-1 provided in an embodiment of the present specification; FIG. 3 is a schematic diagram of the noise transfer function of a different order ΣΔ modulator provided in an embodiment of the present disclosure; Fig. 4 is a schematic diagram of a topology of an LC voltage controlled oscillator provided in an embodiment of the present disclosure; fig. 5 is a schematic diagram of a phase/frequency discriminator circuit configuration provided in the embodiments of the present disclosure; FIG. 6 is a schematic diagram of a circuit of a charge pump provided in an embodiment of the present disclosure; fig. 7 is a schematic diagram of a dc characteristic of a charge pump provided in an embodiment of the present disclosure. Detailed Description For the purposes of promoting an understanding of the principles of the application, reference will now be made to specific embodiments of the application and specific examples, illustrated in the drawings and specific for the purpose of illustration, it will be apparent that the application will be practiced in light of the specific examples, but not in all aspects. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the pr