CN-122001369-A - Time-to-digital converter based on split capacitor and low-jitter digital phase-locked loop

Abstract

The invention discloses a time-to-digital converter based on a split capacitor and a low-jitter digital phase-locked loop, wherein the time-to-digital converter comprises a capacitor array, a time-to-voltage conversion circuit, a charge-discharge power supply and a control signal generation circuit, and the control signal generation circuit receives a reference clock and a frequency division clock thereof and generates a charge control signal and a discharge control signal. And the charge and discharge power supply charges and discharges the capacitor array according to the signals to form residual voltage. The time-voltage conversion circuit is electrically connected with the capacitor array, receives the residual voltage and performs multiple quantization operations on the residual voltage. And each quantization operation is performed by switching the connection state of the reference voltages of the capacitor array to obtain a corresponding residual voltage value, finally obtaining a multi-bit digital code word corresponding to the residual voltage, and generating a conversion completion marking signal to be fed back to the control signal generating circuit so as to reduce the noise of the final digital code word through a plurality of quantization processes.

Inventors

• ZHU SHUYAN
• WU ZIKANG
• ZHENG ZIHAN
• LI YUNCHU

Assignees

• 中山大学

Dates

Publication Date

20260508

Application Date

20260106

Claims (10)

1. 1. The time-to-digital converter based on the split capacitor is characterized by comprising a capacitor array, a control signal generating circuit, a time-to-digital converting circuit and a charge-discharge power supply, wherein the output end of the capacitor array is electrically connected with the input end of the time-to-digital converting circuit; The control signal generating circuit is in signal connection with the time digital conversion circuit and is used for receiving a conversion completion marking signal fed back by the time digital conversion circuit so as to receive a reference clock signal and a frequency division clock signal corresponding to the reference clock signal according to the conversion completion marking signal; The control signal generating circuit generates a charging control signal according to the reference clock signal and generates a discharging control signal according to the frequency division clock signal; The charge-discharge power supply is in signal connection with the control signal generation circuit so as to charge the capacitor array according to the charge control signal and discharge the capacitor array according to the discharge control signal, so that the capacitor array forms residual voltage; The input end of the time-voltage conversion circuit is electrically connected with the output end of the capacitor array and is used for receiving the residual voltage and executing quantization operation on the residual voltage for a plurality of times to obtain digital code words corresponding to the residual voltage each time respectively, obtain multi-bit digital code words corresponding to the residual voltage and generate the conversion completion mark signals, wherein the quantization operation comprises that the time-voltage conversion circuit switches reference voltage connection states of the capacitor array according to the residual voltage so as to obtain the residual voltage corresponding to each reference voltage connection state respectively.
2. 2. The split capacitor based time-to-digital converter of claim 1 wherein said capacitor array comprises a plurality of charging capacitors and a plurality of discharging capacitors that are mirror symmetrical, wherein each of said charging capacitors is connected in series with a charging switch; the lower polar plate of the discharge capacitor is electrically connected with the fixed end of the discharge switch; The first end of the charging switch is electrically connected with the positive reference voltage end; the second end of the charging switch is electrically connected with a negative reference voltage end, the third end of the charging switch is electrically connected with the output end of a charging power supply in the charging and discharging power supply and is used for receiving charging current of the charging power supply, the first end of the discharging switch is electrically connected with the positive reference voltage end, the second end of the discharging switch is electrically connected with the negative reference voltage end, and the third end of the discharging switch is electrically connected with the output end of a discharging power supply in the charging and discharging power supply and is used for receiving discharging current of the discharging power supply; The control end of the third end of the charging switch is in signal connection with the control signal generation circuit and is used for receiving the charging control signal and transmitting the charging current to the charging capacitor according to the charging control signal so as to charge the charging capacitor; the control end of the third end of the discharge switch is in signal connection with the control signal generation circuit and is used for receiving the discharge control signal and transmitting the discharge current to the discharge capacitor according to the discharge control signal so as to charge the discharge capacitor; The upper polar plates of each charging capacitor are electrically connected with each other to form a charging sensing node; the upper polar plates of the discharge capacitors are electrically connected with each other to form a discharge sensing node, and the charge sensing node and the discharge sensing node are respectively and electrically connected with the input end of the time digital conversion circuit; The charging sensing node obtains the energy of a plurality of charging capacitors to form charging voltage; the discharge sensing node acquires the energy of a plurality of discharge capacitors to form a discharge voltage; the charge sensing node and the discharge sensing node serve as output ends of the capacitor array, so that residual voltage is formed according to the charge voltage and the discharge voltage, and the residual voltage is transmitted to the time-digital conversion circuit.
3. 3. The split capacitor based time-to-digital converter of claim 2, wherein the time-to-digital conversion circuit comprises a residual integrator, wherein the residual integrator comprises a switched capacitor integration circuit, a floating inverter amplifier, and an output sampling circuit; The input end of the switch capacitor integrating circuit is electrically connected with the output end of the capacitor array and is used for receiving the residual voltage and carrying out charge integration on the residual voltage to output an integrated voltage, the switch capacitor integrating circuit comprises a first switch, a second switch, a first capacitor and a second capacitor, the positive end of the first switch is electrically connected with the charging sensing node, the positive end of the second switch is electrically connected with the discharging sensing node, the control end of the first switch and the control end of the second switch are used for receiving an integration control clock signal, the positive end of the first capacitor and the negative input end of the floating inverter amplifier are respectively electrically connected with the negative end of the first switch, the positive end of the second capacitor and the positive input end of the floating inverter amplifier are respectively electrically connected with the negative end of the second switch, and when the integration control clock signal is at a high level, the first switch and the second switch are conducted, and the residual voltage is connected to the input end of the floating inverter amplifier through the first capacitor and the second capacitor; the input end of the floating inverter amplifier is electrically connected with the output end of the switched capacitor integration circuit and is used for receiving the integrated voltage and amplifying the integrated voltage so as to output a common-mode voltage; The output sampling circuit is used for sampling the integrated voltage to the input end of the comparator, and comprises a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor and a fourth capacitor, wherein the control end of the third switch and the control end of the fourth switch are used for receiving non-signals of an integration control clock, the negative end of the third switch and the negative end of the fourth switch are electrically connected with a common mode level, the control end of the fifth switch and the control end of the sixth switch are used for receiving the integration control clock, the positive end of the fifth switch is electrically connected with the negative end of the third capacitor, the positive end of the sixth switch is electrically connected with the negative end of the fourth capacitor, and the negative end of the fifth switch and the negative end of the sixth switch are respectively electrically connected with the common mode level; When the integral control clock is at a low level, the third switch and the fourth switch are turned on, the output end of the floating inverter amplifier is connected with the common mode level, the fifth switch and the sixth switch are turned off, and the output sampling circuit is in a reset state; when the integral control clock is at a high level, the third switch and the fourth switch are turned off, and the fifth switch and the sixth switch are turned on; The negative end of the second capacitor, the positive end of the fourth capacitor and the positive end of the fourth switch are respectively and electrically connected with the negative output end of the floating inverter amplifier; the floating inverter amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a seventh switch, an eighth switch and a fifth capacitor, wherein the positive end of the seventh switch is electrically connected with the positive end of the fifth capacitor, the negative end of the seventh switch is electrically connected with a floating power supply positive node, the control end of the seventh switch is used for receiving a non-signal of an integral control clock, the positive end of the eighth switch is electrically connected with the negative end of the fifth capacitor, the negative end of the eighth switch is electrically connected with a floating power supply negative node, and the control end of the eighth switch is used for receiving a non-signal of the integral control clock; When the integral control clock is at a high level, the seventh switch and the eighth switch are respectively connected with the negative node of the floating power supply and the positive node of the floating power supply, and a floating power supply is provided for the floating inverter amplifier; The grid electrode of the first transistor and the grid electrode of the seventh transistor are electrically connected with the positive input end of the floating inverter amplifier, the grid electrode of the second transistor and the grid electrode of the eighth transistor are respectively electrically connected with the negative input end of the floating inverter amplifier, the grid electrode of the third transistor and the grid electrode of the fourth transistor are respectively electrically connected with the positive node of the floating power supply, the grid electrode of the fifth transistor and the grid electrode of the sixth transistor are respectively electrically connected with the negative node of the floating power supply, the source electrode of the first transistor is electrically connected with the negative node of the floating power supply, the drain electrode of the first transistor is electrically connected with the source electrode of the third transistor, the source electrode of the second transistor is electrically connected with the negative node of the floating power supply, the drain electrode of the second transistor is electrically connected with the source electrode of the fourth transistor, the source electrode of the seventh transistor is electrically connected with the positive node of the floating power supply, the drain electrode of the seventh transistor is electrically connected with the negative node of the floating power supply, the source electrode of the eighth transistor is electrically connected with the source electrode of the eighth transistor; The drain electrode of the sixth transistor and the drain electrode of the fourth transistor are respectively and electrically connected with the positive output end of the floating inverter amplifier; the drain electrode of the third transistor and the drain electrode of the fifth transistor are respectively and electrically connected with the negative output end of the floating inverter amplifier; The grid electrode of the third transistor and the grid electrode of the fourth transistor are electrically connected with the positive node of the floating power supply, the grid electrode of the fifth transistor and the grid electrode of the sixth transistor are electrically connected with the negative node of the floating power supply, the source electrode of the seventh transistor and the source electrode of the eighth transistor are electrically connected with the positive node of the floating power supply, and the source electrode of the first transistor and the source electrode of the second transistor are electrically connected with the negative node of the floating power supply.
4. 4. The split capacitor based time-to-digital converter of claim 3 wherein said time-to-digital conversion circuit comprises a dual-input comparator, wherein said dual-input comparator is configured to obtain a residual voltage of said common-mode voltage and an output of said capacitor array to obtain a binary comparison of said common-mode voltage and said residual voltage; The dual input comparator comprises a first input transistor, a second input transistor, a third input transistor, a fourth input transistor, a fifth input transistor, a sixth input transistor, a seventh input transistor, an eighth input transistor, a ninth input transistor, a tenth input transistor, an eleventh input transistor, a twelfth input transistor, a thirteenth input transistor, a first output buffer and a second output buffer; the source electrode of the second input transistor, the third input transistor, the fourth input transistor and the source electrode of the fifth input transistor are respectively and electrically connected with the drain electrode of the first input transistor, the grid electrode of the second input transistor and the grid electrode of the fifth input transistor are respectively and electrically connected to form a first differential input pair of a dual-input comparator, the grid electrode of the third input transistor and the grid electrode of the fourth input transistor are electrically connected to form a second differential input pair of the dual-input comparator, the drain electrode of the third input transistor, the drain electrode of the eighth input transistor and the source electrode of the sixth input transistor are respectively and electrically connected with the drain electrode of the second input transistor, the drain electrode of the fifth input transistor, the drain electrode of the thirteenth input transistor and the source electrode of the seventh input transistor are respectively and electrically connected with the drain electrode of the fourth input transistor, the drain electrode of the tenth input transistor and the source electrode of the eleventh input transistor are respectively connected with the drain electrode of the tenth input transistor, the source electrode of the eleventh input transistor and the source electrode of the eleventh input transistor are respectively connected with the drain electrode of the tenth input transistor and the source electrode of the tenth input transistor; The output ends of the first output buffer and the second output buffer form a differential output end of the dual-input comparator and are used for outputting the binary comparison result.
5. 5. The split capacitor based time-to-digital converter of claim 4, wherein said time-to-digital conversion circuit further comprises a successive approximation logic circuit; the input end of the successive approximation logic circuit is electrically connected with the differential output end of the dual-input comparator and is used for receiving the binary comparison result, and the output end of the successive approximation logic circuit is in signal connection with the control end of the capacitor array and is used for switching the switch connection state of the capacitor array according to the binary comparison result; The successive approximation logic circuit comprises a first AND gate, a first NOR gate, a first inverter, a first exclusive-OR gate, a delay circuit, a plurality of latches and a plurality of triggers; the data input end of each latch and the input end of the first AND gate are respectively and electrically connected with the differential output end; The clock end of each latch is respectively and electrically connected with the output end of the first AND gate so as to receive the effective signal output by the first AND gate; The output end of each latch is connected with the control end of a charging switch or a discharging switch in a signal manner and is used for switching the connection state of the charging switch or the discharging switch; The input end of the delay circuit and the first input end of the first exclusive-OR gate are electrically connected with the output end of the last latch in the latches; The output end of the delay circuit is electrically connected with the second input end of the first exclusive-OR gate and is used for outputting a conversion completion mark signal; The output ends of the latches are electrically connected with the data input ends of the triggers, the clock end of each trigger is electrically connected with the output end of the last latch, and the output ends of the plurality of triggers are used for outputting multi-bit digital code words corresponding to the residual voltage.
6. 6. The split capacitor based time-to-digital converter of claim 5, wherein the latch comprises a first latch transistor, a second latch transistor, a third latch transistor, a fourth latch transistor, a fifth latch transistor, a sixth latch transistor, a seventh latch transistor, an eighth latch transistor, a ninth latch transistor, a tenth latch transistor, an eleventh latch transistor, a twelfth latch transistor, a thirteenth latch transistor; The source electrode of the first latch transistor and the source electrode of the fourth latch transistor are respectively and electrically connected with the power supply voltage, and the grid electrode of the first latch transistor is electrically connected with the grid electrode of the fourth latch transistor; The grid electrode of the fourth latch transistor, the grid electrode of the sixth latch transistor, the grid electrode of the seventh latch transistor and the drain electrode of the second latch transistor are respectively and electrically connected with the drain electrode of the first latch transistor; The source electrode of the second latch transistor is connected with the drain electrode of the third latch transistor, and the grid electrode of the second latch transistor receives a latch clock; the source electrode of the third latch transistor is grounded, the grid electrode of the third latch transistor receives a latch enabling signal, the drain electrode of the fourth latch transistor is electrically connected with the source electrode of the fifth latch transistor, the drain electrode of the fifth latch transistor is electrically connected with the drain electrode of the sixth latch transistor and is used as a latch output end, the grid electrode of the fifth latch transistor receives the latch clock, and the source electrode of the sixth latch transistor is grounded; The source electrode of the eighth latch transistor and the source electrode of the ninth latch transistor are respectively and electrically connected with the drain electrode of the seventh latch transistor; a gate of the eighth latch transistor serves as a first data input of the latch; the gate latched by the ninth transistor is used as a second data input end of the latch; the source electrode of the tenth latch transistor and the source electrode of the eleventh latch transistor are respectively and electrically connected with the grid electrode of the eighth latch transistor; The drain electrode of the tenth latch transistor is used as a first output end of the latch, and the drain electrode of the eleventh latch transistor is used as a second output end of the latch; The source electrode of the twelfth latch transistor and the source electrode of the thirteenth latch transistor are grounded, the grid electrode of the twelfth latch transistor and the grid electrode of the thirteenth latch transistor are respectively connected with the output end of the latch, the drain electrode of the twelfth latch transistor is electrically connected with the first output end, and the drain electrode of the thirteenth latch transistor is electrically connected with the second output end.
7. 7. The split capacitor based time-to-digital converter of any one of claims 2-6, wherein said control signal generation circuit comprises a logic control circuit and a plurality of switch control circuits, wherein each of said charge capacitor switch arrays corresponds to one of said switch control circuits; The logic control circuit comprises a first edge trigger, a second edge trigger, a third edge trigger and an AND gate, wherein the data end of the first edge trigger is connected with a high level, the clock end of the first edge trigger is connected with the time-voltage conversion circuit in a signal manner and is used for receiving a conversion completion marking signal sent by the time-voltage conversion circuit, the reset end of the first edge trigger is connected with the output end of the AND gate, the output end of the first edge trigger is used for outputting a sampling control signal according to the conversion completion marking signal, the data end of the second edge trigger is connected with a high level, the clock end of the second edge trigger is used for receiving a reference clock signal, the reset end of the second edge trigger is connected with the output end of the AND gate, the output end of the second edge trigger is used for outputting the charging control signal according to the reference clock signal, the data end of the third edge trigger is connected with a high level, the clock end of the third edge trigger is used for receiving the clock signal, the reset end of the third edge trigger is connected with the output end of the frequency-dividing trigger is used for outputting the clock signal according to the frequency-dividing signal, and the output end of the clock signal is used for outputting the frequency-dividing signal; The first input end of the AND gate is electrically connected with the output end of the second edge trigger and is used for receiving the charging control signal; The switch control circuit comprises a first NOR gate, a second NOR gate and a third NOR gate, wherein the output end of the first edge trigger and the output end of the successive approximation circuit are respectively connected with the input end of the first NOR gate in a signal mode, so that the first NOR gate receives the sampling control signal and the control signal output by the successive approximation circuit, the output end of the first NOR gate and the output end of the AND gate are respectively connected with the input end of the second NOR gate in a signal mode, so that the second NOR gate receives the charging control signal or the discharging control signal, the output end of the second NOR gate is connected with the control end of the charging switch or the discharging switch in a signal mode, one end of the charging switch or the discharging switch is controlled to be electrically connected with a positive reference voltage end, the output end of the first edge trigger, the output end of the AND gate and the control signal output by the successive approximation circuit are respectively connected with the input end of the third NOR gate in a signal mode, so that the third NOR gate receives the charging control signal or the discharging control signal, the output end of the second NOR gate is connected with the charging switch or the discharging switch in a signal mode, and one end of the charging switch or the discharging switch is controlled to be electrically connected with the positive reference voltage end.
8. 8. A low-jitter digital phase-locked loop, which is characterized by comprising a digital filter, a digital controlled oscillator, a frequency divider and a time-to-digital converter based on split capacitor as claimed in any one of claims 1-7, wherein the input end of the time-to-digital converter is in signal connection with the output end of the frequency divider; the input end of the time-to-digital converter receives a reference clock signal and a frequency division clock signal output by the frequency divider, and is used for acquiring residual voltage corresponding to the reference clock signal and the frequency division clock signal and multi-bit digital code words corresponding to the residual voltage; The input end of the digital filter is in signal connection with the output end of the time-to-digital converter and is used for receiving the multi-bit digital code word and generating a frequency control word corresponding to the multi-bit digital code word; the control end of the numerical control oscillator is in signal connection with the output end of the digital filter and is used for receiving the frequency control word and outputting a frequency multiplication signal corresponding to the reference clock signal according to the frequency control word; The input end of the frequency divider is in signal connection with the output end of the numerical control oscillator and is used for receiving the frequency multiplication signal and dividing the frequency multiplication signal so as to output a frequency division clock signal to the time-to-digital converter.
9. 9. The low jitter digital phase locked loop of claim 8 wherein said digitally controlled oscillator comprises a digital shaping and modulation circuit, a resistive digital to analog conversion circuit, an analog filter circuit, and an lc voltage controlled oscillator circuit; The input end of the digital shaping and modulating circuit is electrically connected with the output end of the digital filter and is used for receiving the frequency control word, carrying out noise shaping and modulating on the frequency control word and outputting a one-bit wide digital code stream; the input end of the resistance type digital-to-analog conversion circuit is electrically connected with the output end of the digital shaping and modulating circuit and is used for converting the one-bit wide digital code stream into an analog voltage signal; the input end of the analog filter circuit is electrically connected with the output end of the resistance type digital-to-analog conversion circuit and is used for filtering high-frequency quantization noise in the analog voltage signal to obtain a filtered analog voltage signal; The voltage control end of the inductance capacitance voltage-controlled oscillation circuit is electrically connected with the output end of the analog filter circuit and is used for generating a frequency multiplication signal with target frequency according to the filtered analog control voltage.
10. 10. The low-jitter digital phase-locked loop of claim 9, wherein the digitally controlled oscillator comprises a digital-to-analog converter, a first oscillating capacitor, a second oscillating capacitor, an oscillating resistor, an adjustable resistor, a first oscillating transistor, a second oscillating transistor, a third oscillating transistor, a fourth oscillating transistor, an inductor, a first varactor and a second varactor, wherein a positive end of the first oscillating capacitor and a positive end of the oscillating resistor are respectively electrically connected with an output end of the digital-to-analog converter, a negative end of the first oscillating capacitor is grounded, a negative end of the second oscillating capacitor is grounded, and a positive end of the second oscillating capacitor, a positive end of the first varactor and a positive end of the second varactor are respectively electrically connected with a negative end of the oscillating resistor; The grid electrode of the second oscillation transistor, the grid electrode of the fourth oscillation transistor, the drain electrode of the third oscillation transistor, the positive end of the inductor, the positive end of the capacitor array and the negative end of the first variable capacitance transistor are respectively and electrically connected with the drain electrode of the first oscillation transistor; the grid electrode of the first oscillating transistor, the grid electrode of the third oscillating transistor, the drain electrode of the fourth oscillating transistor, the negative terminal of the inductor, the negative terminal of the capacitor array and the negative terminal of the second variable capacitance transistor are respectively and electrically connected with the negative terminal of the second oscillating transistor; And the source electrode of the third oscillation transistor and the source electrode of the fourth oscillation transistor are respectively connected with a power supply voltage.

Description

Time-to-digital converter based on split capacitor and low-jitter digital phase-locked loop Technical Field The invention relates to the technical field of phase-locked loops, in particular to a time-to-digital converter based on a split capacitor and a low-jitter digital phase-locked loop. Background Modern wireless communication systems require the use of high order modulation schemes to achieve high data rates, which place extremely high phase noise requirements on the phase locked loop. The digital phase-locked loop not only shows more excellent robustness under the process, voltage and temperature changes, but also has higher reconfigurability and smaller chip area, and can realize seamless integration with a digital signal processing module. However, in-band phase noise of digital phase locked loops is severely limited by quantization errors of the time-to-digital converter, resulting in higher integrated jitter than analog phase locked loops. The performance gap between the analog phase-locked loop and the digital phase-locked loop is a promising work, particularly, the performance of the digital circuit is continuously improved along with the development of integrated circuit technology, and meanwhile, the power consumption is also greatly reduced. In recent years, technologies aimed at achieving fine time resolution have become a research hotspot in the field of time-to-digital converters (TDCs). Among them, the design of the flash type TDC is relatively simple, but its performance is limited by the inherent delay resolution of the inverter. Although the vernier TDC can effectively break through the limitation of single gate delay, the mismatch problem between delay lines still prevents the practical application. Time domain noise shaping TDCs such as gated ring oscillators and noise shaping Bang-Bang phase detectors have the potential to improve TDC resolution. But the 1-bit quantization characteristic inherent to the Bang-Bang phase detector limits the in-band noise performance. In addition, increasing the time domain noise shaping order presents significant challenges. Voltage domain quantization provides an attractive alternative to conventional time domain TDC. However, the existing voltage domain quantization requires higher resolution power consumption cost and has strict requirements on capacitance matching precision. Meanwhile, after the voltage domain quantization technology is introduced, noise introduced by the time-to-digital converter is replaced by the noise to become a main in-band noise source, so that a large amount of noise and unnecessary power consumption overhead are introduced. Disclosure of Invention In order to solve the technical problems, the invention discloses a time-to-digital converter based on a split capacitor and a low-jitter digital phase-locked loop, which are used for reducing noise in the time difference conversion process. In order to achieve the aim, the invention discloses a split capacitor-based time-to-digital converter, which comprises a capacitor array, a control signal generating circuit, a time-to-digital converting circuit and a charge-discharge power supply, wherein the output end of the capacitor array is electrically connected with the input end of the time-to-digital converting circuit; The control signal generating circuit is in signal connection with the time digital conversion circuit and is used for receiving a conversion completion marking signal fed back by the time digital conversion circuit so as to receive a reference clock signal and a frequency division clock signal corresponding to the reference clock signal according to the conversion completion marking signal; The control signal generating circuit generates a charging control signal according to the reference clock signal and generates a discharging control signal according to the frequency division clock signal; The charge-discharge power supply is in signal connection with the control signal generation circuit so as to charge the capacitor array according to the charge control signal and discharge the capacitor array according to the discharge control signal, so that the capacitor array forms residual voltage; The input end of the time-voltage conversion circuit is electrically connected with the output end of the capacitor array and is used for receiving the residual voltage and executing quantization operation on the residual voltage for a plurality of times to obtain digital code words corresponding to the residual voltage each time respectively, obtain multi-bit digital code words corresponding to the residual voltage and generate the conversion completion mark signals, wherein the quantization operation comprises that the time-voltage conversion circuit switches reference voltage connection states of the capacitor array according to the residual voltage so as to obtain the residual voltage corresponding to each reference voltage connection state respectively. According to the