CN-122001371-A - High-precision fractional frequency division circuit based on multiphase clock

CN122001371ACN 122001371 ACN122001371 ACN 122001371ACN-122001371-A

Abstract

The invention discloses a high-precision fractional frequency division circuit based on a multiphase clock, which belongs to the field of integrated circuits and comprises a delay phase-locked loop, a selector, a phase interpolator, a sampling circuit and a digital control circuit. The delay phase-locked loop generates multiphase clock signals, and the multiphase clock signals comprise a voltage-controlled delay line, a phase frequency detector, a charge pump and a low-pass filter, which are formed by cascade connection of delay units, so that jitter accumulation generated by a traditional voltage-controlled oscillator is avoided, the delay phase-locked loop is more suitable for being applied to high-frequency scenes, and the delay phase-locked loop has the advantages of higher locking speed, lower power consumption, easiness in integration and stronger noise resistance. The phase interpolator realizes fractional frequency division by changing the phase of the input signal, each rising edge of the output clock after frequency division is aligned with the edge of the theoretical value, so that the accurate control of the phase is realized, the phase straying can be reduced while the high precision is realized, and the purity of the output signal is optimized.

Inventors

YANG JUNHAO
SHEN SHIYA
JIANG YINGDAN
SHEN JIAN
ZHANG LIYI
QIN ZHANMING

Assignees

中国电子科技集团公司第五十八研究所

Dates

Publication Date: 20260508
Application Date: 20260127

Claims (6)

1. A high precision fractional frequency divider circuit based on a multiphase clock, comprising: a delay phase-locked loop, to which a reference signal is input, generating a multi-phase clock signal; A selector for selecting a group of adjacent clock signals from the clock signals with the same frequency and different phases output by the delay phase-locked loop; a single-ended-to-differential circuit that generates four clock signals from a set of adjacent clock signals output from the selector and inputs the four clock signals to the phase interpolator; the phase interpolator interpolates a phase clock between four paths of input clock signals to realize accurate control of the phase and generate a decimal frequency division clock signal; A digital control circuit for generating control signals and integer frequency division clock signals to the selector and the phase interpolator by the reference signal, the integer frequency division control word and the fractional frequency division control word; And the sampling circuit is used for sampling the integer frequency division clock signal through the integer frequency division clock signal to realize the required fractional frequency division.
2. The multiphase clock based high precision fractional frequency divider circuit of claim 1, wherein the delay locked loop comprises a voltage controlled delay line, a phase frequency detector, a charge pump, a low pass filter, comprising a cascade of delay cells; the voltage-controlled delay line generates a set of multiphase clocks; the phase frequency discriminator compares the phase of the reference signal with the clock output by the last delay unit, and outputs UP, UPN, DN, DNN four paths of pulse signals to control the charge pump to charge or discharge; the current generated by the charge pump is input to a delay unit in the voltage controlled delay line through a low pass filter generating a voltage control signal V Ctrl .
3. The multiphase clock-based high precision fractional frequency divider circuit of claim 2, wherein the delay unit comprises PMOS transistors MP 1-MP 8, NMOS transistors MN 1-MN 8; the sources of the PMOS tubes MP 1-MP 4 are connected with the control voltage V ctrl output by the low-pass filter, the sources of the PMOS tubes MP 5-MP 8 are connected with the power voltage VDD, the sources of the NMOS tubes MN 1-MN 8 are connected with GND, the gates of the PMOS tubes MP1 and MN1 are connected with the input signal V in1 , and the gates of the PMOS tubes MP4 and MN4 are connected with the input signal V in2 ; The drain electrode of the PMOS tube MP1 is connected with the drain electrode of the NMOS tube MN1, and is commonly connected with the grid electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MN5, the drain electrode of the PMOS tube MP6 and the drain electrode of the NMOS tube MN6, the drain electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MN4, and is commonly connected with the grid electrode of the PMOS tube MP3 and the grid electrode of the NMOS tube MN3, the grid electrode of the PMOS tube MP6 and the grid electrode of the NMOS tube MN6, and the drain electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN 5; the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the NMOS tube MN2 and then is connected with the grid electrode of the NMOS tube MN7, the drain electrode of the NMOS tube MN7 is simultaneously connected with the drain electrode of the PMOS tube MP7, the grid electrode of the PMOS tube MP7 and the grid electrode of the PMOS tube MP8, and the drain electrode of the PMOS tube MP8 is connected with the drain electrode of the NMOS tube MN8 and outputs V out .
4. The multiphase clock based high precision fractional frequency divider circuit of claim 2, wherein the charge pump comprises PMOS transistors MP 1-MP 4, NMOS transistors MN 1-MN 4, and an operational amplifier AMP1; The source electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP2 are both connected with the power supply voltage VDD, the grid electrode of the PMOS tube MP1 is connected with the drain electrode of the NMOS tube MN3 after being connected with the drain electrode of the PMOS tube MP1, the grid electrode of the PMOS tube MP2 is connected with the source electrode of the PMOS tube MP3 and the source electrode of the PMOS tube MP4 at the same time, the grid electrode of the PMOS tube MP3 is connected with an UP signal output by a frequency discriminator, the drain electrode of the PMOS tube MP3 is connected with the drain electrode of the NMOS tube MN1 and the output end of the amplifier AMP1 at the same time, and the output end of the amplifier AMP1 is connected with the positive input end of the amplifier AMP 1; The grid electrode of the PMOS tube MP4 is connected with a UPN signal output by the phase frequency detector, the drain electrode of the PMOS tube MP4 is simultaneously connected with the drain electrode of the NMOS tube MN2 and the negative input end of the amplifier AMP1 and outputs as OUT, the grid electrode of the NMOS tube MN1 is connected with a DN signal output by the phase frequency detector, the source electrode of the NMOS tube MN1 is connected with the source electrode of the NMOS tube MN2 and then is connected with the drain electrode of the NMOS tube MN4, the grid electrode of the NMOS tube MN2 is connected with the DNN signal output by the phase frequency detector, the grid electrode of the NMOS tube MN3 is connected with the grid electrode of the NMOS tube MN4 and then is connected with the bias voltage Vb1, and the source electrodes of the NMOS tube MN3 and the NMOS tube MN4 are both connected with GND.
5. The multiphase clock based high precision fractional frequency divider circuit of claim 1, wherein the phase interpolator comprises resistors R1-R2, NMOS transistors MN 1-MN 52, inverters INV 1-INV 16; The first end of the resistor R1 and the first end of the resistor R2 are both connected with the power supply voltage VDD, the second end of the resistor R1 is connected with the drain electrode of the NMOS tube MN1 and output as OUT, the second end of the resistor R2 is connected with the drain electrode of the NMOS tube MN2 and output as OUTN, the grid electrode of the NMOS tube MN1 is connected with the input clock signal Vp1, the source electrode of the NMOS tube MN1 is connected with the source electrode of the NMOS tube MN2 and then connected with the drain electrode of the NMOS tube MN7, the source electrode of the NMOS tube MN5 is connected with the drain electrode of the NMOS tube MN6 and then connected with the grid electrode of the NMOS tube MN7, the source electrode of the NMOS tube MN5 is connected with the bias voltage Vb2, the control signal ctrl_PI 15 is input to the grid electrode of the NMOS tube MN6, the control signal ctrl_PI 15 is input to the grid electrode of the NMOS tube MN5 after passing through the inverter INV1, and the source electrode of the NMOS tube MN6 is connected with GND; The grid electrode of the NMOS tube MN3 is connected with an input clock signal Vp2, the grid electrode of the NMOS tube MN4 is connected with an input clock signal Vn2, the source electrode of the NMOS tube MN3 is connected with the source electrode of the NMOS tube MN4 and then is connected with the drain electrode of the NMOS tube MN7, the source electrode of the NMOS tube MN8 is connected with the drain electrode of the NMOS tube MN10, the source electrode of the NMOS tube MN10 is connected with GND, the drain electrode of the NMOS tube MN10 is connected with the drain electrode of the NMOS tube MN7, the drain electrode of the NMOS tube MN8 is connected with a bias voltage Vb2, a control signal ctrl_PI [14] is input to the grid electrode of the NMOS tube MN9, the control signal ctrl_PI [14] is input to the grid electrode of the NMOS tube MN8 after passing through the inverter INV2, and the source electrode of the NMOS tube MN9 is connected with GND; The three NMOS tubes and one inverter form a unit, sixteen units are arranged in the last unit, the drain electrode of the NMOS tube MN52 is connected with the source electrode of the NMOS tube MN3 and the source electrode of the NMOS tube MN4, the source electrode of the NMOS tube MN50 is connected with the drain electrode of the NMOS tube MN51 and then is connected with the grid electrode of the NMOS tube MN52, the source electrode of the NMOS tube MN52 is connected with GND, the drain electrode of the NMOS tube MN50 is connected with bias voltage Vb2, a control signal ctrl_PI [0] is input to the grid electrode of the NMOS tube MN51, a control signal ctrl_PI [0] is input to the grid electrode of the NMOS tube MN50 after passing through the inverter INV16, and the source electrode of the NMOS tube MN51 is connected with GND.
6. The multi-phase clock-based high precision fractional frequency circuit of claim 1, wherein the digital control circuit comprises a first digital control module, a second digital control module, and a third digital control module, wherein the reference signal, the fractional frequency control word, and the integer frequency division control word are input to the first digital control module, the control signal ctrl_mux to the selector is generated and input to the second digital control module, the sixteen-bit control word pi_sel is input to the second digital control module and the third digital control module, the second digital control module generates the control signal ctrl_pi to the phase interpolator and input to the third digital control module, and the third digital control module generates the integer frequency division signal clk_int to the sampling circuit.

Description

High-precision fractional frequency division circuit based on multiphase clock Technical Field The invention relates to the technical field of integrated circuits, in particular to a high-precision fractional frequency division circuit based on a multiphase clock. Background In recent years, technologies such as wireless communication, satellite positioning, radar navigation, computers and the like are rapidly developed, and higher requirements are put on the transmission speed and quality of data. The phase-locked loop can provide local oscillation signals for the wireless receiving and transmitting system, and indexes such as frequency range, resolution, phase noise and the like of the phase-locked loop can directly influence the performance of the whole system. The minimum resolution of the output frequency of the integer frequency division phase-locked loop is the reference frequency, the fractional frequency division phase-locked loop can realize smaller frequency steps, has higher resolution, can realize finer frequency adjustment, and is widely applied. The delay phase-locked loop adopts a delay line to replace an oscillator to realize clock synchronization on the basis of the phase-locked loop, the phase of a reference clock and the phase of a feedback clock are compared by the phase frequency detector, and a control voltage adjusting delay chain is generated through a charge pump and a low-pass filter. The decimal frequency division based on the delay phase-locked loop does not need to use a delta-sigma modulator, and quantization noise can be restrained while high precision is achieved. Disclosure of Invention The invention aims to provide a high-precision fractional frequency division circuit based on a multiphase clock, which solves the problems in the background technology. In order to solve the technical problem, the present invention provides a high-precision fractional frequency divider circuit based on a multiphase clock, comprising: a delay phase-locked loop, to which a reference signal is input, generating a multi-phase clock signal; A selector for selecting a group of adjacent clock signals from the clock signals with the same frequency and different phases output by the delay phase-locked loop; a single-ended-to-differential circuit that generates four clock signals from a set of adjacent clock signals output from the selector and inputs the four clock signals to the phase interpolator; the phase interpolator interpolates a phase clock between four paths of input clock signals to realize accurate control of the phase and generate a decimal frequency division clock signal; A digital control circuit for generating control signals and integer frequency division clock signals to the selector and the phase interpolator by the reference signal, the integer frequency division control word and the fractional frequency division control word; And the sampling circuit is used for sampling the integer frequency division clock signal through the integer frequency division clock signal to realize the required fractional frequency division. In one embodiment, the delay phase-locked loop comprises a voltage-controlled delay line, a phase frequency detector, a charge pump and a low-pass filter, wherein the voltage-controlled delay line is formed by cascading a plurality of delay units; the voltage-controlled delay line generates a set of multiphase clocks; the phase frequency discriminator compares the phase of the reference signal with the clock output by the last delay unit, and outputs UP, UPN, DN, DNN four paths of pulse signals to control the charge pump to charge or discharge; the current generated by the charge pump is input to a delay unit in the voltage controlled delay line through a low pass filter generating a voltage control signal V Ctrl. In one embodiment, the delay unit comprises PMOS transistors MP 1-MP 8 and NMOS transistors MN 1-MN 8; the sources of the PMOS tubes MP 1-MP 4 are connected with the control voltage V ctrl output by the low-pass filter, the sources of the PMOS tubes MP 5-MP 8 are connected with the power voltage VDD, the sources of the NMOS tubes MN 1-MN 8 are connected with GND, the gates of the PMOS tubes MP1 and MN1 are connected with the input signal V in1, and the gates of the PMOS tubes MP4 and MN4 are connected with the input signal V in2; The drain electrode of the PMOS tube MP1 is connected with the drain electrode of the NMOS tube MN1, and is commonly connected with the grid electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MN5, the drain electrode of the PMOS tube MP6 and the drain electrode of the NMOS tube MN6, the drain electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MN4, and is commonly connected with the grid electrode of the PMOS tube MP3 and the grid electrode of the NMOS tube MN3, the grid electrode of the PMOS tube MP6 and the grid electrode of the NMOS