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CN-122001372-A - Time difference value monoclinic ADC circuit

CN122001372ACN 122001372 ACN122001372 ACN 122001372ACN-122001372-A

Abstract

The application provides a time difference value monoclinic ADC circuit which comprises a slope generator, two phase-locked loops, one phase-locked loop and the other phase-locked loop, wherein the slope generator is connected with a comparator, a time digital converter, a latch and a parallel-serial conversion circuit which are cascaded at the rear end, the two phase-locked loops are connected with the time digital converter, the one phase-locked loop is used for providing a master clock for the time digital converter, the other phase-locked loop is used for providing control voltage for the time digital converter, and error quantization is carried out on double-clock deviation between a clock output by the time digital converter and the master clock through a vernier caliper quantization method so as to calibrate linearity of the ADC circuit. Aiming at the scene of applying the time interpolation monoclinic ADC, the method accurately quantizes the deviation of the double clocks by a vernier caliper quantizing method, and effectively improves the linearity of the monoclinic analog-to-digital converter.

Inventors

  • NIE KAIMING
  • Zou Weipeng
  • JIANG SONG
  • XU JIANGTAO
  • HAN LIQIANG
  • WANG DAN
  • MOU SHUAICHEN
  • FAN WEI

Assignees

  • 天津大学
  • 北京空间机电研究所

Dates

Publication Date
20260508
Application Date
20251031
Priority Date
20251030

Claims (7)

  1. 1. A time difference monoclinic ADC circuit comprising: The slope generator is connected with the comparator, the time-digital converter, the latch and the parallel-serial conversion circuit which are cascaded at the back end; the two phase-locked loops are connected with the time-to-digital converter, one phase-locked loop is used for providing a main clock for the time-to-digital converter, and the other phase-locked loop is used for providing a control voltage for the time-to-digital converter; And carrying out error quantization on the double clock deviation between the clock output by the time-to-digital converter and the main clock by a vernier caliper quantization method so as to calibrate the linearity of the ADC circuit.
  2. 2. The time difference monoclinic ADC circuit of claim 1, wherein: The time-to-digital converter comprises a first TDC module, a second TDC module and a calibration circuit; The first TDC module is internally provided with a first traveling wave counter, the second TDC module is internally provided with a GRO oscillating unit and a second traveling wave counter, the first traveling wave counter and the second traveling wave counter are both connected with the calibration circuit, the GRO oscillating unit is connected with the calibration circuit, and the GRO oscillating unit outputs a GRO_CLK clock; the calibration circuit is configured to control the on-off of the second traveling wave counter between the (M-N+1) th bit and the (M-N) th bit, wherein the control signals are generated by a CNT_CLK clock and a GRO_CLK clock.
  3. 3. The time difference monoclinic ADC circuit of claim 2, wherein the cnt_clk and gro_clk signals satisfy the following relationship: ; ; ; Wherein M, N denotes the number of bits of the counter, m and n are positive integers, and T denotes the clock period.
  4. 4. A time difference monoclinic ADC circuit according to claim 2, wherein: In response to a calibration mode, the calibration circuit operates with the most significant output of the second ripple counter connected to the least significant output of the first ripple counter to form an (M+1) bit ripple counter, and GRO_CLK is the input clock to the least significant output of the ripple counter.
  5. 5. The time difference monoclinic ADC circuit of claim 4, wherein: Upon identifying the falling edge of the STATE signal, the (M-N) th and (M-N+1) th bit counters are turned on to Counting in units, wherein the STATE signal is the level of cnt_clk when the nth gro_clk clock is at a rising edge; And when the falling edge of the STATE signal is identified, transmitting the quantized data and continuing to count, and when the second falling edge of the STATE signal is identified, stopping counting and outputting the quantized data for the second time, and exiting the calibration mode to restore the ADC working mode.
  6. 6. The time difference monoclinic ADC circuit of claim 5, wherein: Subtracting the code value of the first output from the code value of the second output to obtain To 0.5 At the same time, according to the code value difference value of two outputs, judging the double clock deviation Is a sign of (3).
  7. 7. The time difference monoclinic ADC circuit of claim 6, wherein: The formula for the positive sign is as follows: ; The formula when the sign is negative is as follows: 。

Description

Time difference value monoclinic ADC circuit Technical Field The application belongs to the technical field of analog integrated circuits, and particularly relates to a time difference monoclinic ADC circuit. Background Complementary Metal Oxide Semiconductor (CMOS) image sensors are evolving towards high frame rates, high resolution, high accuracy, etc., while monoclinic analog-to-digital converters (Single Slope Analog to Digital Converter, SS ADC) are employed as readout circuit architectures for most CMOS image sensors, which have a profound impact on the performance evolution of CMOS image sensors. The monoclinic ADC mainly comprises a comparator, a counter and a ramp generator, wherein the structure and the performance of the counter play a vital role for the quantization speed of the SS ADC. The conventional SS ADC adopts a travelling wave counter scheme, and the N-bit column parallel SS ADC needs 2 N clock cycles to quantize, so that the development requirements of high frame rate and high precision cannot be met. The SS ADC architecture of the interpolation Time-to-Digital Converter (TDC) solves the problem of high frame rate and high precision compatibility of the conventional SS ADC by using the interpolation TDC technique, but the SS ADC of the conventional interpolation TDC has the problems of high power consumption and large layout area. The column parallel monoclinic ADC based on the gated ring Oscillator (GATED RING Oscillator, GRO) TDC realizes fine quantization through the GRO structure, so that the layout area of the TDC structure can be ensured not to be changed along with the precision of the fine quantization, and meanwhile, the power consumption of the column parallel monoclinic ADC based on the GRO-TDC is effectively reduced by the currently proposed binary search method. The time difference monoclinic ADC adopts a double phase-locked loop (Phase Locked Loop, PLL) structure, wherein one phase-locked loop is used as a main clock for coarse quantization counting, the other phase-locked loop provides control voltage to ensure that GRO generates the same clock as the phase-locked loop, the GRO is used as a fine quantization clock and the main clock to realize fine quantization by using the quantization principle of a vernier caliper, and the difference value of the two clocks is used as quantization precision. However, the quantization mode has two errors due to the limitation of the process technology: (1) The clock difference between the double phase-locked loops has fixed deviation, so that the ratio of the coarse quantization and the fine quantization has deviation, and the linearity of the SS ADC is affected; (2) Clocks generated by the second phase-locked loop and the GRO are not completely consistent, so that deviation exists in the ratio of the thickness quantization, and the linearity of the SS ADC is affected. Disclosure of Invention In view of the above, the present application is directed to a time difference monoclinic ADC circuit for solving the problem of ratio deviation of the coarse and fine quantization of the time difference monoclinic ADC. In order to achieve the above purpose, the technical scheme of the application is realized as follows: the application provides a time difference value monoclinic ADC circuit, which comprises: The slope generator is connected with the comparator, the time-digital converter, the latch and the parallel-serial conversion circuit which are cascaded at the back end; the two phase-locked loops are connected with the time-to-digital converter, one phase-locked loop is used for providing a main clock for the time-to-digital converter, and the other phase-locked loop is used for providing a control voltage for the time-to-digital converter; And carrying out error quantization on the double clock deviation between the clock output by the time-to-digital converter and the main clock by a vernier caliper quantization method so as to calibrate the linearity of the ADC circuit. Further, the time-to-digital converter comprises a first TDC module, a second TDC module and a calibration circuit; The first TDC module is internally provided with a first traveling wave counter, the second TDC module is internally provided with a GRO oscillating unit and a second traveling wave counter, the first traveling wave counter and the second traveling wave counter are both connected with the calibration circuit, the GRO oscillating unit is connected with the calibration circuit, and the GRO oscillating unit outputs a GRO_CLK clock; the calibration circuit is configured to control the on-off of the second traveling wave counter between the (M-N+1) th bit and the (M-N) th bit, wherein the control signals are generated by a CNT_CLK clock and a GRO_CLK clock. Further, the CNT_CLK and GRO_CLK signals satisfy the following relationship: ; ; ; Wherein M, N denotes the number of bits of the counter, m and n are positive integers, and T denotes the clock period. Further,