CN-122001373-A - Feedforward type successive approximation type analog-to-digital converter for mismatch error shaping and mismatch error shaping method thereof

CN122001373ACN 122001373 ACN122001373 ACN 122001373ACN-122001373-A

Abstract

The invention relates to a feedforward type mismatch error shaping successive approximation type analog-to-digital converter and a mismatch error shaping method thereof, wherein the analog-to-digital conversion comprises a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module and a digital logic module, wherein the input ends of the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are connected with input voltages, the output ends of the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are connected with the input ends of the four-input dynamic comparator module, and the output ends of the four-input dynamic comparator module are connected with the digital logic module. The invention provides feedforward capacitor mismatch error shaping based on traditional feedback capacitor mismatch error shaping, and is suitable for a high-precision environment of lower-level plate sampling.

Inventors

XIONG ZHIQI
DENG HONGHUI
TAO CHENGHAO
YIN YONGSHENG
SONG XINGGUO
JIANG HAO

Assignees

合肥工业大学

Dates

Publication Date: 20260508
Application Date: 20260128

Claims (8)

1. The feedforward type mismatch error shaping successive approximation type analog-to-digital converter is characterized by comprising a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module and a digital logic module, wherein the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are all composed of a high-order capacitor MSBCAP and a low-order capacitor LSBCAP; the input ends of the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are connected with input voltages, the output ends of the first CDACP module, the second CDACN module and the second CDACN module are connected with the input ends of the four-input dynamic comparator module, and the output ends of the four-input dynamic comparator module are connected with the digital logic module.
2. The feedforward mismatch error shaping successive approximation analog-to-digital converter of claim 1, wherein MSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch, connected to the digital logic module output terminal through a pre-comparison switch, LSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch, connected to the digital logic module output terminal through a mismatch error shaping MES switch, and output terminal of the first CDACP module is connected to the first input terminal of the four-input dynamic comparator module.
3. The feedforward mismatch error shaping successive approximation analog-to-digital converter of claim 1, wherein MSBCAP input terminal of the first CDACN module is connected to the second input voltage through a sampling switch, connected to the digital logic module output terminal through a pre-comparison switch, LSBCAP input terminal of the first CDACN module is connected to the first input voltage through a sampling switch, connected to the digital logic module output terminal through an MES switch, and output terminal of the first CDACN module is connected to the third input terminal of the four-input dynamic comparator module.
4. The feedforward mismatch error shaping successive approximation analog-to-digital converter of claim 1, wherein MSBCAP input terminal of the second CDACP module is connected to the first input voltage through a sampling switch, connected to the digital logic module output terminal through a pre-comparison switch, LSBCAP input terminal of the second CDACP module is connected to the first input voltage through a sampling switch, connected to the digital logic module output terminal through an MES switch, and output terminal of the second CDACP module is connected to the four-input dynamic comparator module second input terminal.
5. The feedforward mismatch error shaping successive approximation analog-to-digital converter of claim 1, wherein MSBCAP input terminal of the second CDACN module is connected to the second input voltage through a sampling switch, connected to the digital logic module output terminal through a pre-comparison switch, LSBCAP input terminal of the second CDACN module is connected to the first input voltage through a sampling switch, connected to the digital logic module output terminal through an MES switch, and output terminal of the second CDACN module is connected to the fourth input terminal of the four-input dynamic comparator module.
6. A mismatch error shaping method using a feed forward mismatch error shaping successive approximation type analog to digital converter as claimed in any one of claims 1 to 5, comprising: according to the chip selection signals phi c1 and phi c2, the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are controlled to realize cyclic alternating work, the cyclic alternating work is used as an input signal sampling analog-to-digital converter DAC and a mismatch error sampling and dynamic range compensation analog-to-digital converter DAC alternately, and the final conversion result of the ADC is output through the digital logic module.
7. The mismatch error shaping method according to claim 6, wherein implementing a cyclic alternating operation comprises: When the chip select signal Φc1 is high and the chip select signal Φc2 is low, the first CDACP module and the first CDACN module serve as main DACs to sample input signals, the second CDACP module and the second CDACN module serve as MES DACs to sample mismatch errors and compensate dynamic ranges, and when the chip select signal Φc2 is high and the chip select signal Φc1 is low, the second CDACP module and the second CDACN module serve as main DACs to sample input signals, and the first CDACP module and the first CDACN module serve as MES DACs to sample mismatch errors and compensate dynamic ranges.
8. The mismatch error shaping method according to claim 6, wherein the ADC final conversion result The method comprises the following steps: ; Wherein, the In order to be able to input the signal value, In order to be a mismatch error amount, Is a complex variable in the Z-transform domain.

Description

Feedforward type successive approximation type analog-to-digital converter for mismatch error shaping and mismatch error shaping method thereof Technical Field The invention relates to the technical field of analog-digital hybrid integrated circuits, in particular to a feedforward type mismatch error shaping successive approximation type analog-digital converter and a mismatch error shaping method thereof. Background With the rapid development of the fields of the internet of things, medical electronics, industrial automation and the like, the performance requirements of the data converter are continuously improved, and the research of the high-precision analog-to-digital converter (Analog to Digital Converter, ADC) is gradually becoming a hot spot in the academic world and the industry. The successive approximation type (Successive Approximation Register, SAR) ADC is used as a classical ADC architecture, and is widely applied in medium-precision application scenes due to the advantages of simple structure, low power consumption, small area and the like. SAR ADCs offer significant advantages in terms of energy efficiency over other high-precision ADC architectures (e.g., PIPELINE ADC, ΔΣ ADCs). Due to the limitation of factors such as comparator precision and capacitance mismatch, the SAR ADC is difficult to achieve 12bit precision without additional calibration. Among them, DAC capacitance mismatch is one of the main bottlenecks limiting SAR ADC implementation to high accuracy. In a typical SAR ADC, a capacitive DAC array is typically employed to implement the digital-to-analog conversion function. Ideally, each capacitor in the DAC capacitor array should exhibit an accurate binary weight relationship. However, in the actual manufacturing process, random mismatch exists between unit capacitors due to factors such as process deviation, non-uniformity in etching, variation in oxide layer thickness, and the like. Traditional capacitor size increase or complex calibration schemes are difficult to meet the requirements of modern electronic systems on energy efficiency and integration, which promotes the development of innovative technologies such as mismatch error shaping and the like. Both MES (mismatch error shaping) and DEM (dynamic element matching) techniques are key techniques developed to solve the problem of DAC element mismatch in high-precision analog-to-digital converters, and the technical background is derived from the limitations of the conventional calibration method. DEM technology was proposed earlier to suppress harmonic distortion by converting mismatch errors between elements into white noise by using unit elements in the DAC randomly or sequentially, but its circuit complexity and scale area increase exponentially with resolution, and it is difficult to apply to high-order converters. Compared with the DEM technology, the MES technology is more efficient, the noise shaping method uses the noise shaping thought in the delta-sigma modulator, and mismatch errors of the previous period are fed back to the current conversion period, so that the mismatch errors show high-pass characteristics on the frequency domain, and are pushed out of band. And because the mismatch error is represented by extracting the digital code of the capacitor array LSB of the previous period, the mismatch error can be realized by a simple switch circuit, is more suitable for high-order high-precision application, but can introduce new problems such as input range loss, and the like, and because the traditional feedback type MES technology is designed based on the SAR ADC of the upper-level sampling, the mismatch error cannot be applied to the SAR ADC of the lower-level sampling of higher precision. In recent years, scholars have proposed MES application schemes suitable for lower-level plate sampling SAR ADCs, but have limitations due to the multiple increase of input reference noise. Disclosure of Invention The invention aims to provide a feedforward type successive approximation type analog-digital converter for mismatch error shaping and a mismatch error shaping method thereof, which are used for providing feedforward type capacitance mismatch error shaping on the basis of traditional feedback type capacitance mismatch error shaping and are suitable for a high-precision environment of lower-level plate sampling. In order to achieve the above object, the present invention provides the following solutions: A feedforward type mismatch error shaping successive approximation type analog-to-digital converter comprises a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module and a digital logic module, wherein the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are all composed of a high-order capacitor MSBCAP and a low-order capacitor LSBCAP; the input ends of the first CDACP module, the first CDACN modul