CN-122001376-A - High-precision low-delay analog-to-digital converter based on proportional floating inverting amplifier

CN122001376ACN 122001376 ACN122001376 ACN 122001376ACN-122001376-A

Abstract

The invention discloses a high-precision low-delay analog-to-digital converter based on a proportional floating inverting amplifier, which solves the problems that the circuit power consumption cost is high and the linear scaling of the power consumption along with the sampling frequency is difficult to realize in the prior art, and realizes the support of event driving and low power consumption; the digital code filter comprises a first adder, a cascade first-stage integrator, a cascade second-stage integrator and a cascade third-stage integrator, wherein the first adder is used for calculating the difference value between an input signal and an output signal of a feedback DAC module, the cascade first-stage integrator, the cascade second-stage integrator and the cascade third-stage integrator are used for respectively carrying out integral processing on the difference value signal and an upper-stage output signal scaled by a gain coefficient to realize noise shaping, a summing circuit is used for summing the input signal scaled by a feedforward coefficient and the output signal of the three-stage integrator, a single-bit quantizer module is used for quantizing a summation result to generate a digital code stream, the feedback DAC is used for converting the digital code stream into an analog feedback signal, and a cascade integral comb filter is used for filtering the digital code stream and outputting a nyquist rate digital signal.

Inventors

SHEN YUKE
ZHAO YUANHAO
SHEN YI
LIU SHUBIN
DING RUIXUE
ZHU ZHANGMING

Assignees

西安电子科技大学杭州研究院
西安电子科技大学

Dates

Publication Date: 20260508
Application Date: 20260409

Claims (10)

1. A high precision low delay analog to digital converter based on a proportional floating inverting amplifier, comprising: A first adder (107) for receiving an input signal V IN (z) and a first feedback signal and calculating a first difference signal from the input signal V IN (z) and the first feedback signal, wherein the first feedback signal is an output signal of a feedback DAC module (106), the input signal V IN (z) comprises a non-inverting input signal V IP and an inverting input signal V IN ; a first-stage integrator (101) for performing integration processing on the first difference signal to obtain a first-stage output signal; a second-stage integrator (102) for performing integration processing on the first-stage output signal scaled by the gain coefficient between the first stages to obtain a second-stage output signal; a third-stage integrator (103) for integrating the second-stage output signal scaled by the second inter-stage gain factor to obtain a third-stage output signal; The summing circuit is used for summing the input signal V IN (z) scaled by the input feedforward coefficient and the first-stage output signal, the second-stage output signal and the third-stage output signal respectively scaled by different feedforward coefficients to obtain a summation result; -a single bit quantizer module (105) for quantizing the sum result, generating a digital code stream; -a feedback DAC module (106) for converting the digital code stream into an analog signal, provided as the first feedback signal to the first adder (107); And the cascade integrating comb filter (108) is used for filtering the digital code stream and outputting a Nyquist rate digital signal.
2. The high-precision low-delay analog-to-digital converter based on the proportional floating inverting amplifier according to claim 1, wherein the first-stage integrator (101), the second-stage integrator (102) and the third-stage integrator (103) each comprise a dual-level shift module and a proportional floating inverting amplifier (104); The dual-level shift module is used for carrying out level shift processing on the output signal of the proportional floating inverting amplifier (104) through multi-sub-phase time sequence control; The proportional floating inverting amplifier (104) is used as a core operation unit of the integrator and provides a signal amplifying function through an energy storage capacitor power supply mechanism.
3. The high-precision low-delay analog-to-digital converter based on the proportional floating inverting amplifier according to claim 2, wherein the dual-level shift module comprises a first shift circuit of a positive phase output end and a second shift circuit of a negative phase output end; The first shift circuit comprises a first switch S 1 , a first shift capacitor C CLS1 , a second shift capacitor C CLS2 , a second switch S 2 , a third switch S 3 , a fourth switch S 4 and a fifth switch S 5 ; A first end of the first switch S 1 is connected to the normal phase output end V OP of the proportional floating inverting amplifier (104), and a second end of the first switch S 1 is connected to the upper plate of the first shift capacitor C CLS1 and the upper plate of the second shift capacitor C CLS2 ; The lower polar plate of the first shift capacitor C CLS1 is connected to the second end of the third switch S 3 and the second end of the second switch S 2 ; A first end of the third switch S 3 is connected with a positive output end V OP of the proportional floating inverting amplifier (104); The first end of the second switch S 2 is connected to the first end of the fourth switch S 4 with the common mode reference voltage V CM ; The second end of the fourth switch S 4 is connected to the lower plate of the second shift capacitor C CLS2 and the second end of the fifth switch S 5 ; The first end of the fifth switch S 5 is connected with the non-inverting output end of the first-stage integrator (101).
4. The high-precision low-latency analog-to-digital converter based on a proportional floating inverting amplifier according to claim 2, wherein the proportional floating inverting amplifier (104) in the first stage integrator (101) comprises a driver stage floating inverting amplifier and a load stage floating inverting amplifier; the driving stage floating inverting amplifier is used for converting the first difference signal into a first current signal; The load stage floating inverting amplifier is used for providing impedance load for the first current signal for the driving stage floating inverting amplifier, and setting the voltage gain of the proportional floating inverting amplifier (104) through the transistor size proportion between the driving stage floating inverting amplifier and the load stage floating inverting amplifier to obtain a first stage output signal.
5. The high-precision low-latency analog-to-digital converter based on a proportional floating inverter amplifier of claim 4, wherein the driver stage floating inverter amplifier comprises a first PMOS transistor M P1 , a first NMOS transistor M N1 , a second PMOS transistor M P2 , a second NMOS transistor M N2 , and a drive tank sub-circuit; The grid electrode of the first PMOS transistor M P1 is connected with the grid electrode of the first NMOS transistor M N1 and a positive input signal V IP , the source electrode of the first PMOS transistor M P1 and the source electrode of the second PMOS transistor M P2 are connected with a first power supply point of the driving energy storage subcircuit, the drain electrode of the first PMOS transistor M P1 and the drain electrode of the first NMOS transistor M N1 , the grid electrode of a third PMOS transistor M P3 in the load stage floating inverting amplifier, the drain electrode of a third PMOS transistor M P3 in the load stage floating inverting amplifier, the drain electrode of a third NMOS transistor M N3 in the load stage floating inverting amplifier and the grid electrode of a third NMOS transistor M N3 in the load stage floating inverting amplifier are connected with an inverting output end V ON ; The source of the first NMOS transistor M N1 and the source of the second NMOS transistor M N2 are connected to a second power supply node of the driving tank sub-circuit; The grid electrode of the second PMOS transistor M P2 is connected with the grid electrode of the second NMOS transistor M N2 and the inverted input signal V IN , and the drain electrode of the second PMOS transistor M P2 is connected with the drain electrode of the second NMOS transistor M N2 , the grid electrode of the fourth PMOS transistor M P4 in the load stage floating inverting amplifier, the drain electrode of the fourth PMOS transistor M P4 in the load stage floating inverting amplifier, the grid electrode of the fourth NMOS transistor M N4 in the load stage floating inverting amplifier and the drain electrode of the fourth NMOS transistor M N4 in the load stage floating inverting amplifier are all connected with the positive output end V OP .
6. The high-precision low-delay analog-to-digital converter based on the proportional floating inverting amplifier of claim 5, wherein the driving energy storage sub-circuit comprises three driving energy storage units connected in parallel, wherein the driving energy storage units comprise a first energy storage capacitor C R1 , a sixth switch S 6 , a seventh switch S 7 , an eighth switch S 8 and a sixth switch S 9 ; The upper polar plate of the first energy storage capacitor C R1 is connected with the first end of the sixth switch S 6 and the first end of the seventh switch S 7 , and the lower polar plate of the first energy storage capacitor C R1 is connected with the first end of the ninth switch S 9 and the first end of the eighth switch S 8 ; a second end of the sixth switch S 6 is connected with the power supply voltage VDD; The second end of the seventh switch S 7 is connected with the first power supply point; A second end of the ninth switch S 9 is grounded; a second terminal of the eighth switch S 8 is connected to the second supply node.
7. The high-precision low-latency analog-to-digital converter based on a proportional floating inverter amplifier of claim 4, wherein the load stage floating inverter amplifier comprises a third PMOS transistor M P3 , a third NMOS transistor M N3 , a fourth PMOS transistor M P4 , a fourth NMOS transistor M N4 , and a load tank sub-circuit; The grid electrode of the third PMOS transistor M P3 and the drain electrode of the first PMOS transistor M P1 of the driving stage floating inverting amplifier, the drain electrode of the first NMOS transistor M N1 of the driving stage floating inverting amplifier, the drain electrode of the third PMOS transistor M P3 , the drain electrode of the third NMOS transistor M N3 and the grid electrode of the third NMOS transistor M N3 are connected to an inverting output end V ON , and the source electrode of the third PMOS transistor M P3 and the source electrode of the fourth PMOS transistor M P4 are connected to a third power supply node of the load energy storage subcircuit; The source electrode of the third NMOS transistor M N3 and the source electrode of the fourth NMOS transistor M N4 are connected to a fourth power supply node of the load energy storage sub-circuit, and the grid electrode of the third NMOS transistor M N3 is connected to the grid electrode of the third PMOS transistor M P3 ; The drain of the fourth PMOS transistor M P4 is connected to the gate of the fourth PMOS transistor M P4 , the drain of the fourth NMOS transistor M N4 and the gate of the fourth NMOS transistor M N4 , the drain of the second PMOS transistor M P2 of the driver stage floating inverter amplifier and the drain of the second NMOS transistor M N2 of the driver stage floating inverter amplifier are connected to the normal phase output terminal V OP .
8. The high-precision low-delay analog-to-digital converter based on a proportional floating inverting amplifier of claim 7, wherein the load energy storage subcircuit comprises three load energy storage units connected in parallel, wherein the load energy storage units comprise a fourth energy storage capacitor C R4 , an eighteenth switch S 18 , a nineteenth switch S 19 , a twentieth switch S 20 and a twentieth switch S 21 ; The upper polar plate of the fourth energy storage capacitor C R4 is connected with the first end of the eighteenth switch S 18 and the first end of the nineteenth switch S 19 , and the lower polar plate of the fourth energy storage capacitor C R4 is connected with the first end of the twentieth switch S 20 and the first end of the twentieth switch S 21 ; A second end of the eighteenth switch S 18 is connected to the power supply voltage VDD; a second end of the nineteenth switch S 19 is connected to the third power supply point; a second end of the twentieth switch S 21 is grounded; a second end of the twentieth switch S 20 is connected to the fourth power supply node; Fourth energy storage capacitor C R4 , fifth energy storage capacitor C R5 , sixth energy storage capacitor C R6 , thirteenth switch S 13 , fourteenth switch S 14 , fifteenth switch S 15 , sixteenth switch S 16 , seventeenth switch S 17 , eighteenth switch S 18 , nineteenth switch S 19 , and twentieth switch S 20 .
9. The high-precision low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 1, wherein the feedback DAC module (106) comprises a digital selection circuit (1061) and a switch gating circuit (1062); the input end of the digital selection circuit (1061) is connected with the output end of the single-bit quantizer module (105) and is used for generating a switch control signal according to the digital code stream; the control end of the switch gating circuit (1062) is connected with the output end of the digital selection circuit (1061), and the output end of the switch gating circuit (1062) is connected with the input end of the first adder (107) and is used for selecting a reference voltage according to the switch control signal to generate the first feedback signal.
10. The high-precision low-delay analog-to-digital converter based on a proportional floating inverting amplifier according to claim 1, wherein the cascaded integrator-comb filter (108) comprises a multi-stage cascaded integrator-comb filter; The input end of the multistage cascade integrator-comb filter is connected with the output end of the single-bit quantizer module (105); and the output end of the multistage cascade integration comb filter outputs the Nyquist rate digital signal.

Description

High-precision low-delay analog-to-digital converter based on proportional floating inverting amplifier Technical Field The invention relates to the technical field of digital-analog hybrid integrated circuits, in particular to a high-precision low-delay analog-digital converter based on a proportional floating inverting amplifier. Background With the development of digital signal processing technology, the operation precision of a digital system has satisfied complex processing requirements. However, the physical signals in nature exist mainly in analog form, and an analog-to-digital converter serves as a bridge between an analog information domain and a digital signal domain, and functions to convert continuous analog signals into discrete digital signals. In various analog-to-digital converter architectures, the Sigma-Delta analog-to-digital converter can effectively reduce quantization noise in a signal bandwidth through an oversampling technology and a noise shaping technology, so that high resolution is realized. Based on the above characteristics, sigma-Delta analog-to-digital converters are widely used in medical electronics, internet of things (IoT) terminals, and high-precision sensor interface circuits. However, in application scenarios where energy consumption is extremely limited, such as the internet of things and intelligent wearable devices, the design of Sigma-Delta analog-to-digital converters is facing unprecedented challenges. To meet the long endurance requirements of portable devices, analog-to-digital converters must achieve high resolution within the power consumption budget of microwatts and even nanowatts, whereas conventional discrete-time Sigma-Delta analog-to-digital converters typically rely on Operational Transconductance Amplifiers (OTAs) that require continuous static bias currents to maintain gain and bandwidth, resulting in large circuit power consumption overhead and difficulty in achieving linear scaling of power consumption with sampling frequency, severely limiting energy efficiency improvement. Disclosure of Invention The invention solves the problems of high circuit power consumption expenditure and difficult realization of linear scaling of power consumption along with sampling frequency in the prior art by providing the high-precision low-delay analog-to-digital converter based on the proportional floating inverting amplifier, and realizes the support of event driving and low power consumption. The invention provides a high-precision low-delay analog-to-digital converter based on a proportional floating inverting amplifier, which comprises the following components: A first adder 107 for receiving an input signal V IN (z) and a first feedback signal, and calculating a first difference signal according to the input signal V IN (z) and the first feedback signal, wherein the first feedback signal is an output signal of the feedback DAC module 106, the input signal V IN (z) includes a normal phase input signal V IP and an inverted phase input signal V IN; A first-stage integrator 101, configured to perform integration processing on the first difference signal to obtain a first-stage output signal; A second-stage integrator 102, configured to integrate the first-stage output signal scaled by the gain coefficient between the first stages to obtain a second-stage output signal; a third-stage integrator 103, configured to integrate the second-stage output signal scaled by the second-stage gain coefficient to obtain a third-stage output signal; The summing circuit is used for summing the input signal V IN (z) scaled by the input feedforward coefficient and the first-stage output signal, the second-stage output signal and the third-stage output signal respectively scaled by different feedforward coefficients to obtain a summation result; A single bit quantizer module 105 for quantizing the summation result to produce a digital code stream; a feedback DAC module 106 for converting the digital code stream into an analog signal, which is provided as the first feedback signal to the first adder 107; and the cascaded integrator-comb filter 108 is used for filtering the digital code stream and outputting a nyquist rate digital signal. One or more technical schemes provided by the invention have at least the following technical effects or advantages: The invention forms a closed loop feedback structure through the first adder, improves the linearity of the system, and remarkably improves the common mode noise suppression capability by utilizing a fully differential signal processing mechanism; the first-stage integrator realizes first-stage noise shaping on the difference value between an input signal and a feedback signal, pushes quantization noise to a high-frequency area, lays a noise shaping effect for subsequent high-stage shaping, the second-stage integrator further strengthens a noise shaping effect through the second-stage integration, optimizes a signal transfer function, r