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CN-122001377-A - Bypass window type SAR-ADC circuit and module for biological signal acquisition

CN122001377ACN 122001377 ACN122001377 ACN 122001377ACN-122001377-A

Abstract

The invention discloses a bypass window type SAR-ADC circuit and module for biological signal acquisition, and relates to the technical field of successive approximation type analog-to-digital converter design. The invention is improved based on the traditional 10-bit SAR ADC, a composite bypass window comprising a time domain small window and a sub-capacitor switching window is designed, and a plurality of capacitor switches can be selectively skipped through simple combinational logic according to different differential inputs, so that a plurality of high-bit conversion periods are bypassed, the action times of a CDAC part and the working times of a comparator are reduced, unnecessary state switching of the capacitor is avoided, the amplitude of the capacitor switching is greatly reduced, the ADC power consumption is effectively reduced, and the method is very suitable for biological signal acquisition work.

Inventors

  • LI XIN
  • LV YIWEN
  • JIN XIUAN
  • GUAN YONGZHEN
  • DAI CHENGHU
  • HU WEI
  • LIN ZHITING
  • PENG CHUNYU
  • WU XIULONG

Assignees

  • 安徽大学

Dates

Publication Date
20260508
Application Date
20260128

Claims (10)

  1. 1. The Bypass window type SAR-ADC circuit for biological signal acquisition comprises an SAR-ADC main body part, wherein the SAR-ADC main body part comprises 2 switches S 1 ~S 2 , 1 comparator Comp, 1 positive capacitor array CDAC_ip, 1 negative capacitor array CDAC_in and 1 SAR logic, and is characterized by further comprising a time domain window part Bypass and a window judging part judgment; the CDAC_ip and the CDAC_in are respectively provided with 10 capacitors corresponding to the 1 st to 10 th capacitors, and are used for providing a capacitor switching large window with the range of [ -Vref/8 and Vref/8 ]; the Bypass is used for dividing a time domain small window with the range of [ -Vref/16, vref/16] from a capacitance switching large window and judging whether the differential input of Comp falls into the time domain small window or not so as to obtain a corresponding small window judging signal F; Judgment is used for judging whether the differential input of Comp falls into the sub-capacitance switching window with the range of [ -Vref/8, -Vref/16], [ Vref/16, vref/8] to obtain a corresponding large window judging signal SW; The logic is used for selectively skipping a plurality of capacitor switches in CDAC_ip and CDAC_in according to F, SW to reduce power consumption, wherein F=1 and SW=0 indicate that the capacitor falls into a small time domain window and the capacitor with the higher three bits is skipped, F=0 and SW=1 indicate that the capacitor falls into a sub-capacitor switching window and the capacitor with the lower higher bit and the capacitor with the 8 th bit are skipped, and F=0 and SW=0 indicate that the capacitor does not fall into a large capacitor switching window and the capacitor is not skipped.
  2. 2. The bypass window SAR-ADC circuit for biological signal acquisition according to claim 1, wherein cdac_ip comprises 10 capacitors C 0,ip ~C 9,ip , 1 one-out-of-two switch S 0,ip , 9 three one-out-of-two switches S 0,ip ~S 9,ip ; C 0,ip ~C 9,ip is corresponding to the 1 st to 10 th capacitors, the upper polar plates of C i,ip are connected together and connected with the positive input end of Comp, i is 0, 9; C 0,ip 、C 1,ip , C 2,ip , C 3,ip , C 4,ip , C 5,ip , C 6,ip , C 7,ip , C 8,ip , C 9,ip , C64C and C represents a unit capacitance; The input end of S i,ip is connected with the lower polar plate of C i,ip , the output end I of S 0,ip is connected with the ground GND, the output end II is connected with the common mode voltage Vcm, the output end I of S j,ip is connected with the GND, the output end II is connected with the Vcm, and the output end III is connected with the reference voltage Vref, j epsilon [1,9]; The CDAC_in comprises 10 capacitors C 0,in ~C 9,in , 1 two-out-of-one switch S 0,in and 9 three-out-of-one switches S 0,in ~S 9,in ; c 0,in ~C 9,in is corresponding to the 1 st to 10 th capacitors, the upper polar plates of C i,in are connected together and connected with the negative input end of Comp; C 0,in 、C 1,in , C 2,in , C 3,in , C 4,in , C 5,in , C 6,in , C 7,in , C 8,in , C 9,in and C64C respectively; The input end of S i,in is connected with the lower polar plate of C i,in , the output end of S 0,in is connected with GND, the output end of S j,in is connected with Vcm, the output end of S j,in is connected with GND, the output end of S is connected with Vcm, and the output end of S is connected with Vref.
  3. 3. The bypass window SAR-ADC circuit for biological signal acquisition according to claim 2, wherein S 0,ip is controlled by a control signal ND <1>, and wherein if ND <1> is 1, the input of S 0,ip is connected to the output of the second input, and wherein if ND <1> is 0, the input of S 0,ip is connected to the output of the first input; S k,ip is controlled by control signals PD < k+1>, ND < k+1>, k epsilon [1,6], if PD < k+1> is 1 and ND < k+1> is 0, the input end of S k,ip is connected with the first output end, if PD < k+1> is 0 and ND < k+1> is 1, the input end of S k,ip is connected with the third output end, and if PD < k+1> is 0 and ND < k+1> is 0, the input end of S k,ip is connected with the second output end; S 7,ip is controlled by control signals PD <82>, ND <82>, if PD <82> is 1, ND <82> is 0, the input end of S 7,ip is connected with the first output end, if PD <82> is 0, ND <82> is 1, the input end of S 7,ip is connected with the third output end, if PD <82> is 0, ND <82> is 0, the input end of S 7,ip is connected with the second output end; s 8,ip is controlled by control signals PD <81>, ND <81>, if PD <81> is 1, ND <81> is 0, the input end of S 8,ip is connected with the first output end, if PD <81> is 0, ND <81> is 1, the input end of S 8,ip is connected with the third output end, if PD <81> is 0, ND <81> is 0, the input end of S 8,ip is connected with the second output end; S 9,ip is controlled by control signals PD <9>, ND <9>, if PD <9> is 1, ND <9> is 0, the input end of S 9,ip is connected with the first output end, if PD <9> is 0, ND <9> is 1, the input end of S 9,ip is connected with the third output end, if PD <9> is 0, ND <9> is 0, the input end of S 9,ip is connected with the second output end; S 0,in is controlled by a control signal PD <1>, wherein if PD <1> is 1, the input end of S 0,in is connected with the second output end, and if D <1> is 0, the input end of S 0,in is connected with the first output end; S k,in is controlled by PD < k+1>, ND < k+1>, wherein if PD < k+1> is 1 and ND < k+1> is 0, the input end of S k,in is connected with the output end III, if PD < k+1> is 0 and ND < k+1> is 1, the input end of S k,in is connected with the output end I, and if PD < k+1> is 0 and ND < k+1> is 0, the input end of S k,in is connected with the output end II; S 7,in is controlled by PD <82>, ND <82>, if PD <82> is 1, ND <82> is 0, the input end of S 7,in is connected with the output end III, if PD <82> is 0, ND <82> is 1, the input end of S 7,in is connected with the output end I, if PD <82> is 0, ND <82> is 0, the input end of S 7,in is connected with the output end II; S 8,in is controlled by PD <81>, ND <81>, if PD <81> is 1, ND <81> is 0, the input end of S 8,in is connected with the output end III, if PD <81> is 0, ND <81> is 1, the input end of S 8,in is connected with the output end I, if PD <81> is 0, ND <81> is 0, the input end of S 8,in is connected with the output end II; s 9,in is controlled by PD <9>, ND <9>, wherein if PD <9> is 1 and ND <9> is 0, the input end of S 9,in is connected with the output end III, if PD <9> is 0 and ND <9> is 1, the input end of S 9,in is connected with the output end I, and if PD <9> is 0 and ND <9> is 0, the input end of S 9,in is connected with the output end II.
  4. 4. The Bypass window type SAR-ADC circuit for biological signal collection as set forth in claim 3, wherein Bypass comprises 1 exclusive or gate XOR1,2 inverters INV 1-INV 2, 1 Delay chain and 1D flip-flop DFFB; The two input ends of the XOR1 are respectively connected with two output ends of Comp, the input end of the INV1 is connected with a clock signal CLK, the output end is used for outputting an inversion signal CLKB1, the CLKB1 is connected with the control end of Comp and the input end of Delay, the output end of Delay is used for outputting a control signal CLKB2 after the Delay time length T Delay of the CLKB1 is compared with the control signal CLKB2, the D input end of DFFB is connected with the output end of the XOR1, the Q output end is connected with the input end of the INV2, the control end is connected with the CLKB2, and the output end of the INV2 is used for outputting F; Wherein, T Delay is provided with upper and lower limits of the time domain window, F is 1 if the time domain window falls in, and F is 0 if the time domain window does not fall in.
  5. 5. The bypass window type SAR-ADC circuit for biological signal collection as set forth in claim 4 wherein Delay comprises M inverters INV 3 ~ INV M+2 , 1 load capacitor CG, M is an even number, connected in series in sequence; the upper polar plate of CG is connected with the output end of INV 4 , and the lower polar plate is grounded to GND; Wherein, the value of M and/or the capacitance value of CG are/is adjusted to adjust T Delay .
  6. 6. The bypass window SAR-ADC circuit for biological signal acquisition according to claim 4 or 5, wherein the joint comprises 1 exclusive or gate XOR2,1 inverter INVC, 1 AND gate AND; The input end of INVC is connected with F, two input ends of XOR2 are respectively connected with relay signals PD9 AND PD81, the input end of AND is connected with the output end of INVC, the input end of AND is connected with the output end of XOR2, AND the output end is used for outputting SW; If the current falls into the sub-capacitance switching window, F is 0, SW is 1, and if the current does not fall into the sub-capacitance switching window, SW is 0.
  7. 7. The bypass window type SAR-ADC circuit for biological signal collection as set forth in claim 6, wherein the logic comprises 10D flip-flops DFF 0 ~DFF 7 、DFF 82 、DFF 81 、DFF 9 , 1 exclusive OR gate XOR3,5 AND gates ANDB 1-ANDB 5,5 inverters INVB 1-INVB 5,4 switching switches Switch 1-Switch 4, 1 logic control circuit Digtial _con; the two input ends of the XOR3 are respectively connected with the two output ends of the Comp, and the output ends are used for outputting a clock signal CLK1; The first end of Switch1 is connected with the Q output end of DFF 9 and the D input end of DFF 81 , the second end of Switch2 is connected with the second end of Switch2 and the D input end of DFF 7 , the first end of Switch2 is connected with the Q output end of DFF 82 , and switches 1-2 are controlled by F, when F is 1, switch1 is on, switch2 is off, when F is 0, switch1 is off, and Switch2 is on; the input end of INVB1 is connected with F, the output end of INVB1 is connected with the first input end ANDB, the second input end ANDB is connected with a reset signal RST, and the output end is used for outputting the reset signal RST1; The input end of INVB2 is connected with F, the output end of INVB2 is connected with the input end I of ANDB, the input end II of ANDB2 is connected with RST, the output end of INVB3 is connected with the input end I of ANDB3, the input end of INVB3 is connected with SW, the output end of INVB3 is connected with the input end II of ANDB3, and ANDB3 is used for outputting a reset signal RST2; the input end of INVB4 is connected with SW, the output end of INVB4 is connected with the first input end ANDB, the second input end ANDB is connected with RST, and the output end is used for outputting a reset signal RST3; The input end of INVB5 is connected with F, the output end of INVB5 is connected with the first input end ANDB, the second input end ANDB is connected with SW, and the output end is used for outputting a control signal Con; the first end of Switch3 is connected with the Q output end of DFF 81 and the D input end of DFF 82 , the second end is connected with the D input end of DFF 6 and the second end of Switch4, the first end of Switch4 is connected with the Q output end of DFF 7 , switch3 is controlled by SW, when SW is 1, switch3 is off, when SW is 0, switch3 is on, switch4 is controlled by Con, when Con is 1, switch4 is off, and when Con is 0, switch4 is on; the N input end of the DFF 9 is connected with the negative output end of Comp, the P input end is connected with the positive output end of Comp, the time sequence control end is connected with CLK1, the D input end is connected with a power supply VDD, the reset end is connected with a reset signal RST, the PD output end is used for outputting a relay signal PD9, and the ND output end is used for outputting a relay signal ND9; the N input end of the DFF 81 is connected with the negative output end of Comp, the P input end is connected with the positive output end of Comp, the time sequence control end is connected with CLK1, the reset end is connected with RST1, the PD output end is used for outputting a relay signal PD81, and the ND output end is used for outputting a relay signal ND81; The N input end of the DFF 82 is connected with the negative output end of Comp, the P input end is connected with the positive output end of Comp, the time sequence control end is connected with CLK1, the reset end is connected with RST2, the PD output end is used for outputting PD <82>, and the ND output end is used for outputting ND <82>; The N input end of the DFF 7 is connected with the negative output end of Comp, the P input end is connected with the positive output end of Comp, the time sequence control end is connected with CLK1, the reset end is connected with RST3, the PD output end is used for outputting a relay signal PD7, and the ND output end is used for outputting a relay signal ND7; the N input end of the DFF 6 is connected with the negative output end of Comp, the P input end is connected with the positive output end of Comp, the time sequence control end is connected with CLK1, the reset end is connected with RST, the PD output end is used for outputting PD <6>, and the ND output end is used for outputting ND <6>; The N input end of the DFF g is connected with the negative output end of Comp, the P input end is connected with the positive output end of Comp, the time sequence control end is connected with CLK1, the D input end is connected with the Q output end of the DFF g+1 , the reset end is connected with RST, the PD output end is used for outputting PD < g >, and the ND output end is used for outputting ND < g >; Digtial _con is used for generating PD <9> and ND <9> according to F control, generating PD <81> and ND <81> according to F, SW control, and generating PD <7> and ND <7> according to F, PD and PD81 control.
  8. 8. The bypass window SAR-ADC circuit for biological signal acquisition of claim 7, wherein if f=1, then PD <9> =0, ND <9> =0; if f=0, then PD <9> =pd9, ND <9> =nd9; If f=1, sw=0, then PD <81> =0, ND <81> =0; If f=0, sw=1, then PD <81> =0, ND <81> =0; if f=0, sw=0, then PD <81> =pd 81, ND <81> =nd81; If f=0, pd9=1, pd81=0, then PD <7> =0, ND <7> =1; If f=0, pd9=0, pd81=1, then PD <7> =1, ND <7> =0; If f=0, pd9=1, pd81=1, then PD <7> =pd7, ND <7> =nd7; If f=0, pd9=0, pd81=0, then PD <7> =pd7, ND <7> =nd7; if f=1, pd9=1, then PD <7> =1, ND <7> =0; If f=1, pd9=0, then PD <7> =0, ND <7> =1.
  9. 9. The bypass window SAR-ADC circuit for biological signal acquisition according to claim 8, wherein logic is further configured to output a 10-bit quantized result OUT [9:0]; wherein the method comprises the steps of ,OUT[0]=PD<0>;OUT[1]=PD<1>;OUT[2]=PD<2>;OUT[3]=PD<3>;OUT[4]=PD<4>;OUT[5]=PD<5>;OUT[6]=PD<6>;OUT[7]=PD<7>;OUT[8]=PD<82>;OUT[9]=PD<9>.
  10. 10. A bypass window SAR-ADC module for biological signal acquisition, characterized in that it employs the layout of the bypass window SAR-ADC circuit for biological signal acquisition according to any of claims 1-9.

Description

Bypass window type SAR-ADC circuit and module for biological signal acquisition Technical Field The invention relates to the technical field of successive approximation type analog-to-digital converter design, in particular to a bypass window type SAR-ADC circuit for biological signal acquisition, and a bypass window type SAR-ADC module for biological signal acquisition. Background Biological signals such as electrocardio, electroencephalogram, myoelectricity and the like generally have the characteristics of low amplitude of millivolt, frequency lower than 5kHz, slow change and small dynamic range, and therefore strict requirements of low voltage, low power consumption, medium and high precision (10-12 bits) are provided for an analog-to-digital converter (ADC). Successive Approximation (SAR) ADC is a preferred scheme for biological signal detection by virtue of the advantages of simple structure, good compatibility with advanced CMOS technology and controllable power consumption. However, the conventional SAR ADC still faces a plurality of technical bottlenecks when adapting to the characteristics of biological signals, namely 1, the DAC capacitor array of the conventional SAR ADC is required to switch capacitors bit by bit to complete conversion, biological signals are in a small-amplitude fluctuation state most of the time, frequent switching of high-order large capacitors causes a great amount of power consumption waste, 2, the conventional switching algorithms such as Monotonic and the like can cause continuous change of common mode level in the conversion process to cause dynamic imbalance of a comparator and deteriorate linearity, the VCM-based algorithm can stabilize the common mode level, but requires additional reference voltage circuits to increase hardware and power consumption expenditure, 3, the conventional algorithm is required to complete all N-bit conversion periods no matter the amplitude of input signals, and for biological signals with low change rate, part of high-order conversion steps are redundant, so that energy is wasted and conversion efficiency is reduced. In general, the use of conventional SAR ADCs for bio-signal detection suffers from redundant power consumption. Disclosure of Invention Based on this, it is necessary to provide a bypass window type SAR-ADC circuit, module for biosignal acquisition, in order to solve the problem of redundant power consumption in biosignal detection using conventional SAR ADCs. The invention is realized by adopting the following technical scheme: In a first aspect, the invention provides a Bypass window type SAR-ADC circuit for biological signal acquisition, which comprises an SAR-ADC main body part, a time domain window part Bypass and a window judging part eudgment. The SAR-ADC main body part comprises 2 switches S 1~S2, 1 comparator Comp, 1 positive capacitor array CDAC_ip, 1 negative capacitor array CDAC_in and 1 SAR logic. The CDAC_ip and the CDAC_in are respectively provided with 10 capacitors corresponding to the 1 st to 10 th capacitors, and are used for providing a large capacitor switching window with the range of [ -Vref/8 and Vref/8 ]. The Bypass is used for dividing a time domain small window with the range of [ -Vref/16, vref/16] from the capacitance switching large window and judging whether the differential input of Comp falls into the time domain small window or not so as to obtain a corresponding small window judging signal F. The value is used for judging whether the differential input of Comp falls into the sub-capacitance switching window with the range of [ -Vref/8, -Vref/16], [ Vref/16, vref/8] to obtain a corresponding large window judging signal SW. The logic is used for selectively skipping a plurality of capacitor switches in CDAC_ip and CDAC_in according to F, SW to reduce power consumption, wherein F=1 and SW=0 indicate that the capacitor falls into a small time domain window and the capacitor with the higher three bits is skipped, F=0 and SW=1 indicate that the capacitor falls into a sub-capacitor switching window and the capacitor with the lower higher bit and the capacitor with the 8 th bit are skipped, and F=0 and SW=0 indicate that the capacitor does not fall into a large capacitor switching window and the capacitor is not skipped. Implementation of such a bypass window SAR-ADC circuit for biosignal acquisition is in accordance with methods or processes of embodiments of the present disclosure. In a second aspect, the present invention discloses a bypass window SAR-ADC module for biosignal acquisition, employing the layout of the bypass window SAR-ADC circuit for biosignal acquisition as disclosed in the first aspect. Implementation of such a bypass window SAR-ADC module for biosignal acquisition is in accordance with methods or processes of embodiments of the present disclosure. Compared with the prior art, the invention has the following beneficial effects: 1. The invention is improved based on the tradition