CN-122001394-A - High anti-interference bus self-adaptive decoding circuit and equipment

Abstract

The invention relates to a high anti-interference bus self-adaptive decoding circuit and equipment, which comprises a signal sampling branch connected between a bus input end and a comparator, wherein a signal feedback branch is connected in series on the signal sampling branch, the signal feedback branch comprises a first resistor and an NMOS tube which are connected in parallel, the NMOS tube works in a linear resistor area, the original signal sampling branch is connected in series with the signal feedback branch formed by connecting the first resistor and the NMOS tube in parallel, an original fixed decoding reference generation mechanism is transformed into an adaptive dynamic reference generation mechanism, vdrop is not a fixed compromise value on design any more, but can be intelligently adjusted according to the actual working condition of a bus, and the dynamic characteristic effectively relieves the inherent contradiction between the loading capacity and the anti-interference capacity in the traditional circuit, so that a two-bus receiving end can stably and reliably work in a wider load range and a harsher noise environment.

Inventors

• Zou Danxia
• WU SIXIN

Assignees

• 深圳市鹏芯数据技术有限公司

Dates

Publication Date

20260508

Application Date

20260129

Claims (4)

1. 1. A high anti-interference bus self-adaptive decoding circuit comprises a signal sampling branch circuit connected between a bus input end and a comparator, and is characterized in that a signal feedback branch circuit is connected in series on the signal sampling branch circuit, the signal feedback branch circuit comprises a first resistor and an NMOS tube which are connected in parallel, and the NMOS tube works in a linear resistor area.
2. 2. The high-immunity bus adaptive decoding circuit of claim 1, wherein the signal feedback branch further comprises a second resistor, a third resistor, and a fourth resistor; The G electrode of the NMOS tube is connected with the second resistor and the third resistor, the S electrode of the NMOS tube is grounded, the D electrode of the NMOS tube is connected with the fourth resistor, the other end of the second resistor is connected with one end of the first resistor, the other end of the fourth resistor is connected with the other end of the first resistor, and the other end of the third resistor is grounded.
3. 3. The high-immunity bus adaptive decoding circuit as set forth in claim 1 wherein the signal sampling branch comprises a fifth resistor, a diode, and a capacitive storage node connected in sequence, the signal feedback branch being connected in series between the capacitive storage node and a comparator.
4. 4. A high-immunity bus device, wherein the high-immunity bus device is provided with the high-immunity bus adaptive decoding circuit as set forth in any one of claims 1-3.

Description

High anti-interference bus self-adaptive decoding circuit and equipment Technical Field The invention relates to the technical field of two-bus communication, in particular to a high-anti-interference bus self-adaptive decoding circuit and equipment. Background The two buses are BUS technology for carrying communication and power supply functions at the same time, the performance of a receiving end is of critical importance, in the prior art, a mature and widely used receiving front-end circuit is shown in fig. 1, and the core design concept of the circuit is that attenuation signals are received through a BUS input end (BUS), and the capacitor of a node SC is rapidly charged by utilizing the unidirectional conduction characteristic of a diode under light load (namely, less BUS load), so that a reference voltage Vsc representing a BUS logic high level 'VH' is stored. Typically, vsc≡VH-Vdrop, where Vdrop is a fixed voltage drop across the diode, this reference voltage Vsc is fed into the back-end comparator together with the real-time bus voltage Vbus (i.e. the actual potential of node SC) for differential comparison, and when the comparison satisfies the flip condition, its output RX will generate a digital signal for decoding by the micro-downstream controller (MCU). The waveform diagram shown in fig. 2 clearly illustrates this process, and in an ideal case, the BUS input waveform (BUS) is attenuated in amplitude (high level lower than nominal VH and low level higher than GND) due to line impedance, load, etc., but the receiving end can accurately recover the regular digital waveform (RX) by comparing with the dynamic reference "SC stores high level plane line". However, it is this decoding mechanism that aims to accommodate the attenuation of the bus voltage that brings about an inherent contradiction that is difficult to reconcile, namely that the bus load carrying capacity and the anti-jamming capacity cannot be optimized at the same time, and the specific contradiction analysis is as follows: To ensure that the decoding capability (load capability) under heavy load conditions is ensured in that the actual high level VH of the bus drops to a minimum value VHmin and the difference in level (VH-VL) becomes smaller due to the larger voltage drop of the supply current across the bus resistance when the bus load is larger, it is necessary to satisfy Vsc-VL > Vth, i.e. VHmin-Vdrop-VL > Vth, in order to ensure that the comparator can still reliably flip at this time, it can be deduced that: VHmin VL > Vdrop+Vth (1) This shows that the value of (VHmin-VL) should be as small as possible in order to accommodate heavier loads (i.e. allow VHmin to be lower). In order to ensure the anti-interference capability under the light load condition, when the bus load is light, the capacitive reactance formed by the line distributed capacitance is smaller, and the bus is easier to couple external electromagnetic interference. As shown in fig. 2, this disturbance often appears as superimposed sine wave noise (peak-to-peak vpp_noise) on the bus, during the high level of the bus, the disturbance may cause the instantaneous voltage Vbus to be pulled down to VH-vpp_noise/2, at which time, if Vsc-vbus=vh-Vdrop- (VH-vpp_noise/2) =vpp_noise/2-Vdrop > Vth, the comparator will flip erroneously, resulting in decoding errors, and the condition to avoid errors is simplified: Vpp_noise/2< Vdrop+Vth (formula 2) The limit condition for stable operation of the system, which is available in combination of formula (1) and formula (2), is vpp_noise/2< VHmin-VL, which means that the value of (VHmin-VL) should be as large as possible in order to resist larger noise (i.e. allow vpp_noise to be larger). On the one hand, in order to improve the carrying capacity of the bus (the measurement index is (VHmax-VHmin)/Iq, and in the case that VHmax and static current Iq are fixed, the lower the VHmin can be, the better the expected (VHmin-VL) is, and on the other hand, in order to enhance the anti-interference capacity of the bus under light load, the higher the expected (VHmin-VL) is, the better the expected (VHmin-VL) is. The fundamental contradiction makes the traditional receiving circuit based on the SC storing high level difficult to ensure stable decoding and simultaneously combine the performance requirements of large load driving and strong noise suppression when facing complex and changeable application scenes, so that a high anti-interference bus self-adaptive decoding circuit capable of realizing different anti-interference capabilities under different bus load conditions to combine the requirements of bus loading capability and communication quality (signal integrity) is needed. Disclosure of Invention The invention aims to solve the technical problems of the prior art, and provides a high anti-interference bus self-adaptive decoding circuit, high anti-interference bus equipment and a high anti-interference bus self-adaptive decoding circuit