CN-122001507-A - Synchronous serial communication system, synchronous serial communication module, synchronous serial communication method, and computer-readable storage medium

CN122001507ACN 122001507 ACN122001507 ACN 122001507ACN-122001507-A

Abstract

The invention provides a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method and a computer readable storage medium. The synchronous serial communication system includes a master configured to provide a clock signal, and a plurality of cascaded slaves, each slave including a first serial interface through which the first slave is coupled to the master, and a second serial interface through which the second serial interface of the slave located upstream is coupled to the first serial interface of the slave located downstream for adjacent slaves, each slave synchronously receiving the clock signal from the master through the first serial interface and the second serial interface. The synchronous serial communication system of the invention has the advantages that the SPI only communicates between the host and the first slave and between the two adjacent slaves, the number of the slaves is not limited by the number of the chip selection signals which can be provided by the SPI host, the communication speed is not limited by the furthest-distance slaves, the number of the slaves is not limited, the communication speed can be improved, and the communication efficiency is improved.

Inventors

YE JUN
CHEN MEILIANG

Assignees

施耐德电气工业公司

Dates

Publication Date: 20260508
Application Date: 20241101

Claims (16)

1.A synchronous serial communication system, comprising: a host configured to provide a clock signal, and A plurality of cascaded slaves, wherein each slave comprises a first serial interface and a second serial interface, the first slave is coupled to the master through the first serial interface, the second serial interface of the slave positioned at the upstream is coupled with the first serial interface of the slave positioned at the downstream for the adjacent slaves, Wherein each slave synchronously receives the clock signal from the master through the first serial interface and the second serial interface.
2. The synchronous serial communication system of claim 1, wherein the host includes a host clock interface, a host data output interface, and a host data input interface, the first serial interface includes a first slave clock interface, a first slave data input interface, and a first slave data output interface, the second serial interface includes a second slave clock interface, a second slave data output interface, and a second slave data input interface, the first slave clock interface, the first slave data input interface, and the first slave data output interface of the first slave are respectively connected to the host clock interface, the host data output interface, and the host data input interface of the host, and for an adjacent slave, the second slave clock interface, the second slave data output interface, and the second slave data input interface of the second serial interface of the upstream slave are respectively coupled to the first slave clock interface, the first slave data input interface, and the first slave data output interface of the first serial interface of the downstream slave.
3. The synchronous serial communication system of claim 2, wherein the first slave clock interface and the second slave clock interface of each slave are coupled to a master clock interface of the master to synchronously receive the clock signals.
4. The synchronous serial communication system of claim 3, wherein the master comprises a master control chip, each slave comprises a slave control chip, and each slave's slave control chip is coupled to the master control chip and to the respective first and second serial interfaces.
5. The synchronous serial communication system of claim 4, wherein the plurality of slaves includes at least two slaves.
6. The synchronous serial communication system of claim 5, wherein the received information of a downstream slave is forwarded to the downstream slave in stages via its upstream slave.
7. The synchronous serial communication system of claim 6, wherein the received information of the slave includes its operation mode information and operation mode information of a slave downstream thereof.
8. The synchronous serial communication system according to claim 6 or 7, wherein the reception information of the slave further includes its IO output data and the IO output data of the slave downstream thereof.
9. The synchronous serial communication system according to claim 5, wherein the transmission information of the slave located downstream is forwarded to the master in stages via the slave located upstream thereof.
10. A synchronous serial communication system according to claim 9, wherein the transmission information of the slave includes its own parameter information and its own parameter information of the downstream slave, and/or its operation state information and its operation state information of the downstream slave.
11. The synchronous serial communication system of claim 10, wherein the slave's transmit information further includes its IO input data and its downstream slave's IO input data.
12. The synchronous serial communication system of claim 11, wherein the slave's transmit information further comprises end information received through the second data input interface of the last slave and transmitted through the last slave's slave control chip to its first data output interface and forwarded to the master in stages via its upstream slave.
13. The synchronous serial communication system of claim 12, wherein the master is configured to receive the self parameter information and the end information and determine the number of slaves based on the self parameter information and the end information.
14. A synchronous serial communication module, comprising: a first serial interface adapted to connect to a host or a serial communication module upstream thereof; A second serial interface adapted to connect the serial communication module downstream thereof, And the first slave clock interface of the first serial interface and the second slave clock interface of the second serial interface are further adapted to connect to a host to synchronously receive clock signals provided by the host.
15. A synchronous serial communication method performed by the synchronous serial communication system according to any one of claims 1-13.
16. A computer readable storage medium comprising computer executable instructions stored thereon, which when executed by a processor implement the synchronous serial communication method of claim 15.

Description

Synchronous serial communication system, synchronous serial communication module, synchronous serial communication method, and computer-readable storage medium Technical Field The present invention relates generally to the field of communications technologies, and in particular, to a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method, and a computer readable storage medium. Background SPI (Serial Peripheral Interface) is a high-speed, full duplex, synchronous communications bus. The SPI adopts a Master-Slave control mode (Master-Slave) architecture, and comprises a host computer and a plurality of slaves, wherein each Slave comprises an SPI interface, and the SPI interface of the host computer polls the SPI interface of each Slave, so that communication between the host computer and the slaves is realized. The communication mode has two defects, namely, if each SPI slave machine is gated through one chip selection signal, the number of the slave machines is limited by the number of the chip selection signals which can be provided by the SPI master machine, and if each slave machine is cascaded through a single SPI interface, the communication speed is limited by the number of the slave machines, the more the number of the slave machines, the slower the communication speed, and the communication delay is accumulated. Accordingly, a need exists for a new synchronous serial communication system and method that overcomes the above-described drawbacks. The matters in the background section are only those known to the inventors and do not, of course, represent prior art in the field. Disclosure of Invention In view of one or more of the problems of the prior art, the present invention provides a synchronous serial communication system comprising a master configured to provide a clock signal, and a plurality of cascaded slaves, wherein each slave comprises a first serial interface through which the first slave is coupled to the master, and a second serial interface, for adjacent slaves, of which the second serial interface of the slave located upstream is coupled to the first serial interface of the slave located downstream, wherein each slave receives the clock signal from the master synchronously through the first serial interface and the second serial interface. Optionally, the host includes a host clock interface, a host data output interface, and a host data input interface, the first serial interface includes a first slave clock interface, a first slave data input interface, and a first slave data output interface, the second serial interface includes a second slave clock interface, a second slave data output interface, and a second slave data input interface, the first slave clock interface, the first slave data input interface, and the first slave data output interface of the first slave are respectively connected to the host clock interface, the host data output interface, and the host data input interface of the host, and for an adjacent slave, the second slave clock interface, the second slave data output interface, and the second slave data input interface of the second serial interface of the slave located upstream are respectively coupled to the first slave clock interface, the first slave data input interface, and the first slave data output interface of the first serial interface of the slave located downstream. Optionally, the first slave clock interface and the second slave clock interface of each slave are coupled to a master clock interface of the master to synchronously receive the clock signals. Optionally, the host includes a host control chip, each slave includes a slave control chip, and the slave control chip of each slave is coupled to the host control chip and to the respective first serial interface and the second serial interface. Optionally, wherein the plurality of slaves includes at least two slaves. Optionally, the received information of the slave located downstream is forwarded to the slave located downstream step by step via the slave located upstream. Optionally, the receiving information of the slave includes the operation mode information of the slave and the operation mode information of the slave downstream of the slave. Optionally, the receiving information of the slave further includes the IO output data of the slave and the IO output data of the slave downstream of the slave. Alternatively, the transmission information of the slave located downstream is forwarded to the master stage by stage via the slave located upstream. Optionally, the sending information of the slave comprises own parameter information and own parameter information of the slave downstream of the slave, and/or working state information of the slave and working state information of the slave downstream of the slave. Optionally, the sending information of the slave further includes the IO input data of the slave and the IO input