CN-122001524-A - Modem chip, system on chip including modem chip, and data processing method

Abstract

A modem chip, a system on a chip including the modem chip, and a data processing method are provided. The modem chip is capable of receiving a codeword comprising a transport block, the transport block comprising a plurality of code blocks, the modem chip comprising hybrid automatic repeat request (HARQ) processing circuitry configured to perform HARQ-based processing operations comprising a first cyclic redundancy check and a second cyclic redundancy check for the codeword, and an internal memory storing data generated during the second cyclic redundancy check. The plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and the internal memory includes a plurality of memory elements allocated to the plurality of memory management groups in a one-to-one correspondence.

Inventors

• PEI ZHIMIN

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20250815

Priority Date

20241105

Claims (20)

1. 1. A modem chip capable of receiving a codeword comprising a transport block, the transport block comprising a plurality of code blocks, the modem chip comprising: Hybrid automatic repeat request processing circuitry configured to perform hybrid automatic repeat request based processing operations including a first cyclic redundancy check and a second cyclic redundancy check for the codeword, and An internal memory configured to store data generated during the second cyclic redundancy check, Wherein the hybrid automatic repeat request processing circuit comprises: A code block processing circuit configured to decode the plurality of code blocks into decoded code blocks and perform a first cyclic redundancy check on each of the decoded code blocks, and A codeword processing circuit configured to perform a second cyclic redundancy check on the decoded transport block by generating a target block corresponding to the decoded code block based on a modulo operation using a polynomial for the second cyclic redundancy check, Wherein the plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and Wherein the internal memory includes a plurality of memory elements allocated to a plurality of memory management groups in a one-to-one correspondence.
2. 2. The modem chip of claim 1, wherein each of the plurality of memory elements is configured to have a capacity corresponding to a data size of a remainder, the remainder being generated by a modulo operation for one target block.
3. 3. The modem chip of claim 1, wherein, A first memory management group among the plurality of memory management groups includes a first code block and a second code block sequentially arranged, A first memory element of the plurality of memory elements is assigned to a first memory management group, The codeword processing circuit is further configured to access the first memory element during a time period in which the second cyclic redundancy check is performed, based on a result of the first cyclic redundancy check for the decoded first code block and the decoded second code block included in the decoded code block and memory management information corresponding to the first memory management group, and The memory management information includes an arrangement order between the first code block and the second code block and an address of the first memory element.
4. 4. The modem chip of claim 3, wherein the codeword processing circuit is further configured to write a first remainder generated by a modulo operation for a first target block included in the target block to the first memory element, the first target block corresponding to the decoded first code block having passed the first cyclic redundancy check, and to rewrite a second remainder generated by a modulo operation for a second target block included in the target block to the first memory element, the second target block corresponding to the decoded second code block having passed the first cyclic redundancy check.
5. 5. The modem chip of claim 3, wherein the codeword processing circuit is further configured to write a first remainder generated by a modulo operation for a first target block included in the target block to the first memory element, the first target block corresponding to a decoded first code block that has passed the first cyclic redundancy check, and skip writing of a second remainder generated by a modulo operation for a second target block included in the target block, the second target block corresponding to a decoded second code block that has not passed the first cyclic redundancy check.
6. 6. The modem chip of claim 5, wherein, The code block processing circuit is further configured to receive the retransmitted second code block, and The codeword processing circuit is further configured to rewrite, to the first memory element, a third remainder generated by a modulo operation for a third target block included in the target block, the third target block corresponding to the retransmitted second code block that passed the first cyclic redundancy check.
7. 7. The modem chip of claim 3, further comprising a register circuit comprising a first register, Wherein the codeword processing circuit is configured to selectively access the first register based on a result of the first cyclic redundancy check and the memory management information during a time period in which the second cyclic redundancy check is performed.
8. 8. The modem chip of claim 7, wherein the codeword processing circuit is further configured to skip writing of a first remainder generated by a modulo operation for a first target block included in the target block, the first target block corresponding to a decoded first code block that fails a first cyclic redundancy check, and to write a second remainder generated by a modulo operation for a second target block included in the target block, the second target block corresponding to a decoded second code block that has passed a second cyclic redundancy check, to the first memory element.
9. 9. The modem chip of claim 8, wherein, The code block processing circuit also receives the retransmitted first code block, and The codeword processing circuit is further configured to write third intermediate data to the first register, the third intermediate data being generated by a modulo operation on a third target block included in the target block, the third target block corresponding to the retransmitted first code block that passed the first cyclic redundancy check.
10. 10. The modem chip of claim 7, wherein the internal memory has a storage capacity greater than a storage capacity of the register circuit.
11. 11. The modem chip of claim 1, wherein a memory management group unit of the plurality of memory management groups corresponds to a code block group comprising a plurality of code blocks for a retransmission.
12. 12. The modem chip of claim 1, wherein the codeword processing circuit is further configured to determine whether the second cyclic redundancy check has passed based on a final remainder corresponding to a last target block among the target blocks.
13. 13. The modem chip of claim 1, wherein the code block processing circuit is further configured to store a decoded second code block that has passed the first cyclic redundancy check among the decoded code blocks in the external memory based on the decoded first code block that has not passed the first cyclic redundancy check among the decoded code blocks.
14. 14. The modem chip of claim 1, Wherein the decoded code block includes a first code block, a second code block, and a third code block sequentially processed by a code block processing circuit, and Wherein the target block includes: The first target block comprises a first code block and a zero bit; a second target block including a second code block, zero bits, and a first remainder obtained by dividing the first target block by the polynomial, and And a third target block including a third code block, zero bits, and a second remainder obtained by dividing the second target block by the polynomial.
15. 15. A modem chip capable of communicating with an external memory via a bus, the modem chip comprising: A hybrid automatic repeat request processing circuit configured to perform a hybrid automatic repeat request based processing operation including a first cyclic redundancy check and a second cyclic redundancy check for a codeword including a transport block, the transport block including a plurality of code blocks, and An internal memory configured to store data generated during the second cyclic redundancy check, Wherein the hybrid automatic repeat request processing circuit comprises: a code block processing circuit configured to decode the plurality of code blocks into decoded code blocks, perform a first cyclic redundancy check on the decoded code blocks, and store the decoded code blocks that pass the first cyclic redundancy check included in the decoded code blocks into an external memory, and Codeword processing circuitry configured to perform a second cyclic redundancy check on the decoded transport blocks by performing a modulo operation on each of the decoded code blocks, respectively, to generate a target block, Wherein the plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and Wherein the internal memory includes a plurality of memory elements allocated to the plurality of memory management groups in a one-to-one correspondence.
16. 16. The modem chip of claim 15, wherein the codeword processing circuit is further configured to store a first effective remainder among remainders corresponding to the target block and generated by the modulo operation in the internal memory based on the memory management information about the plurality of memory management groups, and Wherein the first significant remainder further corresponds to a decoded code block that passes the first cyclic redundancy check.
17. 17. The modem chip of claim 16, wherein the memory management information includes a mapping table including code blocks, an arrangement order of the code blocks included in the memory management group, and addresses of memory elements allocated to the code blocks.
18. 18. The modem chip of claim 16, further comprising a register circuit comprising at least one register configured for use in a second cyclic redundancy check, Wherein the codeword processing circuit is further configured to store a second effective remainder among remainders corresponding to the target block in the at least one register based on the memory management information.
19. 19. The modem chip of claim 18, wherein, The internal memory corresponds to the volatile memory, and The at least one register corresponds to a flip-flop or a latch.
20. 20. A system on a chip, comprising: A modem including an internal memory including a plurality of memory elements and configured to support a hybrid automatic repeat request function, and A processor configured to perform certain data processing operations, Wherein the modem is further configured to store, in the internal memory, intermediate data generated in a second cyclic redundancy check performed for the transport block by using a target block corresponding to the decoded first code block having passed the first cyclic redundancy check based on the memory management information corresponding to the first code block, and Wherein the memory management information includes an arrangement order of the first code blocks in a memory management group including the first code blocks and addresses of memory elements allocated to the first code blocks.

Description

Modem chip, system on chip including modem chip, and data processing method The present application is based on and claims priority of korean patent application No. 10-2024-0155667 filed in the korean intellectual property office on 5 th month 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Aspects of the inventive concept relate to a modem chip forming a modem integrated circuit capable of decoding a codeword and performing Cyclic Redundancy Check (CRC) on the decoded codeword, and a system on a chip including the modem integrated circuit. Background In a communication system, a transmitting device may transmit a codeword including a transport block (e.g., a payload) composed of code blocks to a receiving device. The codeword may include CRC bits for performing CRC (hereinafter, referred to as first CRC) on each code block and Transport Block Cyclic Redundancy Check (TBCRC) bits for performing CRC (hereinafter, referred to as second CRC) on the transport block. The modem of the receiving apparatus may determine whether the received codeword has been successfully decoded by decoding the received codeword into units of decoded code blocks, performing a first CRC on each of the decoded code blocks, and performing a second CRC on the decoded transport block. When there is a code block that has failed in the first CRC among the decoded code blocks, the modem may request the transmitting apparatus to retransmit the corresponding code block in units of code block groups, and the decoded code block that has passed the first CRC may be stored in the external memory. Thereafter, the modem may read the decoded code block from the external memory, generate a decoded transport block by concatenating the decoded result of the retransmitted code block with the read decoded code block, and perform a second CRC on the decoded transport block. Because the external memory is also used by a processor other than the modem of the receiving device, the bus connecting the external memory to each of the modem and the processor may be switched to a busy state by the processor, and thus communication through the bus between the modem and the external memory may be temporarily difficult. Further, as the data size of the decoded code block stored in the external memory gradually increases with advances in communication technology, the modem's access to the external memory for the second CRC may increase the load on the bus and the external memory. Therefore, the second CRC of the decoded transport block by the modem may not be completed within a preset time, resulting in degradation of the performance of the modem. Disclosure of Invention Aspects of the inventive concept provide a modem chip and a system on chip including the modem chip, the modem chip being capable of performing a second Cyclic Redundancy Check (CRC) based on a remainder of a target block corresponding to a code block of a codeword, and storing intermediate data generated in the second CRC in an internal memory. Aspects of the inventive concept provide a modem chip and a system on chip including the modem chip, the modem chip storing intermediate data in an internal memory based on memory management information to effectively use the internal memory in the second CRC. According to an aspect of the inventive concept, there is provided a modem chip capable of receiving a codeword including a transport block including a plurality of code blocks, the modem chip including hybrid automatic repeat request (HARQ) processing circuitry configured to perform HARQ-based processing operations including a first cyclic redundancy check and a second cyclic redundancy check for the codeword, and an internal memory storing data generated during the second cyclic redundancy check. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks into decoded code blocks and perform a first cyclic redundancy check on each of the decoded code blocks, and a codeword processing circuit configured to perform a second cyclic redundancy check on a decoded transport block by generating a target block corresponding to the decoded code block based on a modulo operation using a polynomial for the second cyclic redundancy check. The plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and the internal memory includes a plurality of memory elements allocated to the plurality of memory management groups in a one-to-one correspondence. According to another aspect of the inventive concept, there is provided a modem chip capable of communicating with an external memory via a bus, the modem chip comprising a HARQ processing circuit configured to perform a HARQ-based processing operation comprising a first cyclic redundancy check and a second cyclic redundancy check for a codeword comprising a transport block, the transport block