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CN-122001705-A - Anti-collision control circuit and method for wireless communication signals

CN122001705ACN 122001705 ACN122001705 ACN 122001705ACN-122001705-A

Abstract

The invention discloses an anti-collision control circuit and method of wireless communication signals, which relate to the technical field of wireless communication, wherein the anti-collision control circuit comprises a RISC-V core processor, a bus routing circuit, an APB bus, a digital baseband circuit, a RIB bus, a read-only memory and a random access memory, wherein the bus routing circuit is respectively connected with the RISC-V core processor, the APB bus and the RIB bus, the RIB bus is respectively connected with the read-only memory and the random access memory, and the APB bus is connected with the digital baseband circuit; the RISC-V core processor comprises an instruction fetching circuit, a decoding circuit and an executing circuit, wherein the digital baseband circuit comprises a transmitting link circuit, a receiving link circuit, a multiplexing circuit, a baseband controller and an anti-collision algorithm hardware accelerating circuit. The method and the device ensure flexible and configurable algorithm, obviously reduce calculation delay and improve the recognition efficiency and the system throughput performance in a multi-label dense scene.

Inventors

  • Chen Zhankang
  • WU YUCHAO
  • WANG DEMING

Assignees

  • 华南师范大学

Dates

Publication Date
20260508
Application Date
20260302

Claims (10)

  1. 1. The anti-collision control circuit of the wireless communication signal is characterized by comprising a RISC-V core processor, a bus routing circuit, an advanced peripheral APB bus, a digital baseband circuit, a RIB bus, a read-only memory and a random access memory, wherein the bus routing circuit is respectively connected with the RISC-V core processor, the APB bus and the RIB bus, the RIB bus is respectively connected with the read-only memory and the random access memory, and the APB bus is connected with the digital baseband circuit; The RISC-V core processor comprises an instruction fetching circuit, a decoding circuit and an executing circuit, wherein the decoding circuit is respectively connected with the instruction fetching circuit and the executing circuit; The digital baseband circuit comprises a transmitting link circuit, a receiving link circuit, a multiplexing circuit, a baseband controller and an anti-collision algorithm hardware acceleration circuit, wherein the multiplexing circuit is respectively connected with the transmitting link circuit, the receiving link circuit, the baseband controller and the anti-collision algorithm hardware acceleration circuit.
  2. 2. The collision avoidance control circuit of a wireless communication signal according to claim 1 wherein said receive chain circuit comprises a receive control circuit, a frame synchronization decoding circuit, an FM0 decoding circuit, said frame synchronization decoding circuit being connected to said receive control circuit and FM0 decoding circuit, respectively.
  3. 3. The collision avoidance control circuit of a wireless communication signal according to claim 1 wherein said transmit link circuit comprises a transmit control circuit, a frame synchronization coding circuit, a pulse width coding PIE coding circuit, said frame synchronization coding circuit being connected to said transmit control circuit and PIE coding circuit, respectively.
  4. 4. The collision avoidance control circuit of a wireless communication signal according to claim 1 wherein said multiplexing circuit comprises a parallel-to-serial converter, a cyclic redundancy check, CRC-5, check circuit, and a CRC16 check circuit, said parallel-to-serial converter being connected to said CRC-5 check circuit and CRC16 check circuit, respectively.
  5. 5. The anti-collision control circuit of a wireless communication signal according to claim 1, wherein the anti-collision algorithm hardware acceleration circuit comprises a subframe statistics counter and shift lookup table unit, a tag number estimation circuit and an optimal Q value update controller, the tag number estimation circuit being respectively connected with the subframe statistics counter and shift lookup table unit and the optimal Q value update controller.
  6. 6. A collision avoidance control method for a wireless communication signal, the method being implemented based on the collision avoidance control circuit for a wireless communication signal according to any one of claims 1 to 5, the method comprising: initializing a digital baseband circuit based on a RISC-V core processor, determining parameter information based on the digital baseband circuit, and identifying tag information based on the parameter information; in the process of identifying the tag information, monitoring a time slot return signal, and carrying out time slot state judgment based on the time slot return signal to obtain a time slot state judgment result; performing label number estimation based on the time slot state judgment result to obtain label number estimation information; And carrying out target Q value analysis by utilizing a preset interval based on the label quantity estimation information to obtain a target Q value, determining an anti-collision recognition result based on the target Q value, and outputting a control signal based on the anti-collision recognition result.
  7. 7. The method for collision avoidance control of a wireless communication signal according to claim 1, wherein said performing a slot state decision based on the slot return signal to obtain a slot state decision result comprises: Performing tag response judgment based on the time slot return signal to obtain a tag response judgment result; And carrying out time slot state judgment based on the label response judgment result to obtain a time slot state judgment result.
  8. 8. The method for collision avoidance control of a wireless communication signal according to claim 1, wherein the performing tag number estimation based on the slot state decision result to obtain tag number estimation information comprises: Counting a successful time slot counter based on the time slot state judgment result to obtain a first counting result; counting an idle time slot counter based on the time slot state judgment result to obtain a second counting result; counting collision time slot counters based on the time slot state judgment result to obtain a third counting result; and performing label number estimation based on the first statistical result, the second statistical result and the third statistical result to obtain label number estimation information.
  9. 9. The method according to claim 1, wherein the performing Q value analysis using a preset interval based on the tag number estimation information to obtain a target Q value comprises: Determining a preset interval, and comparing the label quantity estimation information with the preset interval to obtain a comparison result; and carrying out Q value analysis based on the comparison result to obtain a target Q value.
  10. 10. The method for collision avoidance control of a wireless communication signal according to claim 9, wherein said determining a preset interval comprises: Updating the controller setting LUT lookup table based on the optimal Q value; And searching the LUT lookup table for a section to obtain a system efficiency optimal label number section, and determining a preset section based on the system efficiency optimal label number section.

Description

Anti-collision control circuit and method for wireless communication signals Technical Field The present invention relates to the field of wireless communications technologies, and in particular, to an anti-collision control circuit and method for a wireless communication signal. Background The ultra-high frequency wireless communication technology is widely applied to various Internet of things scenes such as warehouse logistics, intelligent retail and the like, and can realize non-contact automatic identification of remote and batch targets. With the expansion of the application scale of the internet of things, the ultrahigh frequency wireless communication chip often needs to rapidly inventory hundreds or thousands of electronic tags in an extremely short time window. However, all tags share the same wireless channel, when a plurality of tags respond simultaneously in the same time slot, signals of the tags can be overlapped and interfered in the air, so that the ultrahigh frequency wireless communication chip cannot correctly demodulate data, and the signal collision phenomenon severely restricts the recognition speed and the throughput rate of a circuit. The existing collision algorithm often controls the frame length by adjusting the parameter Q, and dynamically adjusts the Q value according to the feedback of the current time slot. Although the algorithm is simple and feasible, the algorithm adopts a blind adjustment strategy with fixed step length, and lacks global perception of the number of the residual labels. When the number of the labels fluctuates severely, the algorithm often falls into parameter oscillation for a long time, so that serious idle time slot waste or continuous collision is caused, and the convergence speed is extremely slow. In order to solve the problem of slow convergence of the standard algorithm, a corresponding hardware scheme is proposed in the industry to fully solidify the algorithm logic in the circuit. Although the response speed of the scheme is extremely high, the flexibility is lacking, and once the application scene changes or protocol standards evolve, the cured chip cannot upgrade or adjust parameters. Disclosure of Invention The invention aims to overcome the defects of the prior art, and provides an anti-collision control circuit and method for wireless communication signals, which can ensure flexible and configurable algorithm, obviously reduce calculation delay and improve the recognition efficiency and system throughput performance in a multi-label dense scene. In order to solve the technical problems, the invention provides an anti-collision control circuit of wireless communication signals, which comprises a RISC-V core processor, a bus routing circuit, an advanced peripheral APB bus, a digital baseband circuit, a RIB bus, a read-only memory and a random access memory, wherein the bus routing circuit is respectively connected with the RISC-V core processor, the APB bus and the RIB bus, the RIB bus is respectively connected with the read-only memory and the random access memory, and the APB bus is connected with the digital baseband circuit; The RISC-V core processor comprises an instruction fetching circuit, a decoding circuit and an executing circuit, wherein the decoding circuit is respectively connected with the instruction fetching circuit and the executing circuit; The digital baseband circuit comprises a transmitting link circuit, a receiving link circuit, a multiplexing circuit, a baseband controller and an anti-collision algorithm hardware acceleration circuit, wherein the multiplexing circuit is respectively connected with the transmitting link circuit, the receiving link circuit, the baseband controller and the anti-collision algorithm hardware acceleration circuit. Optionally, the receiving link circuit includes a receiving control circuit, a frame synchronization decoding circuit, and an FM0 decoding circuit, where the frame synchronization decoding circuit is connected to the receiving control circuit and the FM0 decoding circuit, respectively. Optionally, the transmission link circuit includes a transmission control circuit, a frame synchronization coding circuit, and a pulse width coding PIE coding circuit, where the frame synchronization coding circuit is connected to the transmission control circuit and the PIE coding circuit respectively. Optionally, the multiplexing circuit includes a parallel-to-serial converter, a cyclic redundancy check (CRC-5) check circuit and a CRC16 check circuit, and the parallel-to-serial converter is respectively connected with the CRC-5 check circuit and the CRC16 check circuit. Optionally, the anti-collision algorithm hardware acceleration circuit includes a subframe statistics counter and shift lookup table unit, a tag number estimation circuit and an optimal Q value update controller, where the tag number estimation circuit is connected with the subframe statistics counter and shift lookup table unit and t