CN-122001722-A - Fractional feedforward equalization transmitting circuit and transmitter

CN122001722ACN 122001722 ACN122001722 ACN 122001722ACN-122001722-A

Abstract

The invention provides a fractional feedforward equalization transmitting circuit and a transmitter, wherein in the fractional feedforward equalization transmitting circuit, a line multiplexing module is used for outputting high-speed multiplexed data to a retimer, the retimer is used for delaying and outputting a time sequence high-speed signal to a feedforward equalization module, a clock distribution circuit is used for outputting a delay control signal to the feedforward equalization module, and the feedforward equalization module is used for distributing the time sequence high-speed signal to a plurality of taps according to the control signal, respectively carrying out fractional equalization on the taps according to the delay control signal, and synthesizing and outputting a full-rate data signal. According to the invention, the window time of the time sequence high-speed signal is distributed to each tap through the delay control signal output by the clock distribution circuit, so that each tap can slide back and forth freely, and fractional balance is realized.

Inventors

LIU XIAOLONG
WANG BIN

Assignees

南方科技大学

Dates

Publication Date: 20260508
Application Date: 20260410

Claims (10)

1. A fractional feedforward equalization transmitting circuit is characterized by comprising a line multiplexing module, a retimer, a feedforward equalization module and a clock distribution circuit, wherein, The signal access end of the line multiplexing module is respectively connected with a plurality of low-speed data, and the signal output end of the line multiplexing module is connected with the re-timer and is used for carrying out line multiplexing on the low-speed data to obtain a plurality of high-speed multiplexing data, and outputting the high-speed multiplexing data to the re-timer; the re-timer is connected with the feedforward equalization module and is used for delaying the high-speed multiplexed data and outputting a time sequence high-speed signal to the feedforward equalization module; The clock distribution circuit is connected with the feedforward equalization module and is used for generating a delay control signal and outputting the delay control signal to the feedforward equalization module; The feedforward equalization module is connected with a control word signal, is used for distributing the time sequence high-speed signal to a plurality of taps according to the control word signal, and respectively carrying out fractional equalization on the taps according to a delay control signal to synthesize and output a full-rate data signal.
2. The fractional feed-forward balanced transmitting circuit of claim 1, further comprising an output matching network, a signal access terminal of the output matching network being connected to the feed-forward balanced module for impedance matching the full-rate data signal and transmitting an balanced matched signal.
3. The fractional feed-forward balanced transmitting circuit of claim 1, wherein the feed-forward balanced module comprises a plurality of feed-forward balanced sections, each of the feed-forward balanced sections being arranged in parallel, the feed-forward balanced sections being connected to the control word signal and distributing a time-sequential high-speed signal to one of the taps in accordance with the control word signal.
4. The fractional feedforward equalization transmitting circuit of claim 3, wherein the feedforward equalization module includes six feedforward equalization segments, each of the feedforward equalization segments being arranged in parallel, the feedforward equalization segments being coupled to the control word signal and being distributed to one of the first tap, the second tap, and the third tap based on the control word signal; the feedforward equalization section comprises a plurality of clock selectors, a plurality of data selectors, a plurality of pulse signal generators and a multiplexing driver, wherein, Each clock selector is respectively connected with the control word signal and the pulse signal generator, and outputs a window clock signal to the pulse signal generator according to the control word signal, wherein the window clock signal is used for controlling clock windows of a first tap, a second tap and a third tap; Each data selector is respectively connected with the control word signal and the pulse signal generator, and is used for sampling a time sequence high-speed signal in a clock window according to the control word signal, gating any one of a first tap, a second tap and a third tap, and outputting a window data signal to the pulse signal generator; The pulse signal generator is connected with the multiplexing driver and is used for outputting a unit pulse signal to the multiplexing driver according to the window clock signal and the window data signal, wherein the number of the clock selector, the number of the data selector and the number of the pulse signal generator are the same; and the multiplexing driver performs current summation on the unit pulse signals output by the pulse signal generators to obtain the full-rate data signals.
5. The fractional feed forward balanced transmit circuit of claim 4, wherein the feed forward balanced section further comprises a bias selector coupled to the multiplexing driver for outputting a bias adjustment voltage to the multiplexing driver; The multiplexing driver adjusts the swing and linearity of the full-rate data signal according to the bias adjustment voltage.
6. The fractional feedforward equalization transmitting circuit of claim 1, wherein the clock distribution circuit includes a quadrature clock generator, a phase error calibrator, a duty cycle calibrator, a voltage controlled delay unit, a buffer, and a frequency divider, wherein, The quadrature clock generator is connected with the phase error calibrator and is used for outputting a quadrature clock signal to the phase error calibrator; The phase error calibrator is connected with the duty cycle calibrator, and is used for performing phase error adjustment on the quadrature clock signal and outputting a phase calibration signal to the duty cycle calibrator; The duty ratio calibrator is respectively connected with the buffer and the voltage-controlled delay unit, and is used for performing duty ratio error adjustment on the phase calibration signal and outputting a calibration quadrature signal to the voltage-controlled delay unit and the buffer; The voltage-controlled delay unit is connected with the feedforward equalization module and is used for adjusting the delay time of the calibration orthogonal signal and outputting the delay control signal to the feedforward equalization module; The output end of the buffer is connected with the retimer and is used for amplifying the calibration orthogonal signal and outputting a feedback orthogonal clock to the retimer; The input end of the frequency divider is connected with the buffer, the output end of the frequency divider is connected with the line multiplexing module and is used for dividing the frequency of the feedback quadrature clock and outputting a driving clock signal to the line multiplexing module and used for driving the line multiplexing module to carry out line multiplexing on the low-speed data.
7. The fractional feedforward equalization transmitting circuit of claim 6, wherein the voltage controlled delay unit comprises a first voltage controlled delay line, a second voltage controlled delay line, and a third voltage controlled delay line, the first voltage controlled delay line, the second voltage controlled delay line, and the third voltage controlled delay line being respectively coupled to the duty cycle calibrator.
8. The fractional feed forward balanced transmit circuit of claim 6, wherein the line multiplexing module is a 32:4 multiplexer, the 32:4 multiplexer comprising a 32:16 multiplexer, a 16:8 multiplexer, and an 8:4 multiplexer, the 32:16 multiplexer, the 16:8 multiplexer, and the 8:4 multiplexer being cascaded, the 32:16 multiplexer accessing 32 low speed data, the 8:4 multiplexer being connected to the retimer and outputting 4 high speed multiplexed data to the retimer, the high speed multiplexed data comprising a most significant bit value and a least significant bit value, the weight of the most significant bit value being configured to be twice the least significant bit value.
9. The fractional feedforward equalization transmitting circuit according to claim 1, wherein the retimer comprises a first differential I trigger, a second differential I trigger, a third differential I trigger, a fourth differential I trigger, a differential Q trigger, a differential IB trigger and a differential QB trigger, wherein the first differential I trigger, the second differential I trigger, the third differential I trigger and the fourth differential I trigger are arranged in parallel and are respectively connected with high-speed multiplexed data, the high-speed multiplexed data comprise first high-speed multiplexed data, second high-speed multiplexed data, third high-speed multiplexed data and fourth high-speed multiplexed data, one end of the first differential I trigger is connected with the first high-speed multiplexed data, the other end of the first differential I trigger is connected with the feedforward equalization module, one end of the second differential I trigger is connected with the second high-speed multiplexed data, the other end of the second differential I trigger is connected with one end of the differential Q trigger, the other end of the differential IB trigger is connected with the differential Q trigger, the other end of the differential I trigger is connected with the differential QB trigger, and the other end of the differential I trigger is connected with the differential QB trigger.
10. A transmitter comprising a fractional feed forward equalisation transmitting circuit according to any one of claims 1 to 9.

Description

Fractional feedforward equalization transmitting circuit and transmitter Technical Field The invention relates to the technical field of high-speed data communication, in particular to a fractional feedforward equalization transmitting circuit and a transmitter. Background With the rapid development of artificial intelligence, the throughput requirements of data centers are increased explosively, and the realization of high-speed and low-power-consumption wired transceivers is particularly important. Four-order pulse amplitude modulated (4 Pulse Amplitude Modulation,PAM4) signals are signaled using four different signal levels, each symbol period can represent two bits of logic information, doubling the data rate. In order to further improve linearity of a PAM4 signal eye diagram, an existing feedforward equalizer (Feed Forward Equalizer, FFE) based on a digital-analog mixed architecture adopts a fractional equalization wired transmitter, so that the problem of limited equalization capacity is solved, reconfiguration of the number of taps is supported, and flexibility is enhanced. However, this architecture requires a large number of retimers to retime, resulting in an increase in power consumption overhead of the overall transmitter, and an increase in layout area on the chip, resulting in a decrease in overall energy efficiency of the transmitter. Accordingly, the prior art is still in need of improvement and development. Disclosure of Invention In view of the defects in the prior art, the invention aims to provide a fractional feedforward equalization transmitting circuit and a transmitter, so as to solve the problems of complex structure, large on-chip layout area and high production and processing cost of the existing fractional equalization mode. The technical scheme of the invention is as follows: the invention provides a fractional feedforward equalization transmitting circuit, which comprises a line multiplexing module, a retimer, a feedforward equalization module and a clock distribution circuit, wherein, The signal access end of the line multiplexing module is respectively connected with a plurality of low-speed data, and the signal output end of the line multiplexing module is connected with the re-timer and is used for carrying out line multiplexing on the low-speed data to obtain a plurality of high-speed multiplexing data, and outputting the high-speed multiplexing data to the re-timer; the re-timer is connected with the feedforward equalization module and is used for delaying the high-speed multiplexed data and outputting a time sequence high-speed signal to the feedforward equalization module; The clock distribution circuit is connected with the feedforward equalization module and is used for generating a delay control signal and outputting the delay control signal to the feedforward equalization module; The feedforward equalization module is connected with a control word signal, is used for distributing the time sequence high-speed signal to a plurality of taps according to the control word signal, and respectively carrying out fractional equalization on the taps according to a delay control signal to synthesize and output a full-rate data signal. The invention further provides an output matching network, wherein a signal access end of the output matching network is connected with the feedforward equalization module and is used for carrying out impedance matching on the full-rate data signal and transmitting an equalization matching signal. According to the further arrangement of the invention, the feedforward equalization module comprises a plurality of feedforward equalization segments, each feedforward equalization segment is arranged in parallel, the feedforward equalization segments are connected with a control word signal, and the timing sequence high-speed signal is distributed to one of the taps according to the control word signal. The invention further provides that the feedforward equalization module comprises six feedforward equalization segments, wherein each feedforward equalization segment is arranged in parallel, is connected with a control word signal and is distributed to one of a first tap, a second tap and a third tap according to the control word signal; the feedforward equalization section comprises a plurality of clock selectors, a plurality of data selectors, a plurality of pulse signal generators and a multiplexing driver, wherein, Each clock selector is respectively connected with a control word signal and is respectively connected with the pulse signal generator, and outputs a window clock signal to the pulse signal generator according to the control word signal, wherein the window clock signal is used for controlling clock windows of a first tap, a second tap and a third tap; Each data selector is respectively connected with a control word signal and is respectively connected with the pulse signal generator, and is used for sampling a time sequence high-speed si