CN-122001836-A - Transmission chip, transmission method, chip system, optical module and transmission device

Abstract

The application relates to a transmission chip, a transmission method, a chip system, an optical module and a transmission device, and relates to the technical field of chips. The transmission chip comprises a plurality of receiving ends and a plurality of receiving channels, wherein the plurality of receiving channels comprise a first receiving channel and a second receiving channel, the first receiving channel comprises a clock input end, the second receiving channel comprises a clock output end, the plurality of receiving ends are coupled with the plurality of receiving channels in a one-to-one correspondence manner, and the clock input end of the first receiving channel is coupled with the clock output end of the second receiving channel. Thus, the starting time of the transmission channel where the first receiving channel is located can be reduced.

Inventors

• WANG DONG
• LEI ZHANGWEI
• DUI KAI
• LIANG GUI
• SUN DESHENG
• CHEN CHUANGLU

Assignees

• 华为技术有限公司

Dates

Publication Date

20260508

Application Date

20241107

Claims (20)

1. 1. The transmission chip is characterized by comprising a plurality of receiving ends and a plurality of receiving channels, wherein the plurality of receiving channels comprise a first receiving channel and a second receiving channel, the first receiving channel comprises a clock input end, and the second receiving channel comprises a clock output end; the plurality of receiving ends are coupled with the plurality of receiving channels in a one-to-one correspondence manner; The clock input end of the first receiving channel is coupled with the clock output end of the second receiving channel.
2. 2. The transmit chip of claim 1, wherein the first receive channel and the second receive channel each comprise a clock circuit; The clock input end of the first receiving channel is coupled with the clock circuit of the first receiving channel, and the clock output end of the second receiving channel is coupled with the clock circuit of the second receiving channel.
3. 3. The transmit chip of claim 2, wherein the first receive channel and the second receive channel each comprise a buffer; The clock input end of the first receiving channel is coupled with the clock circuit of the first receiving channel through the buffer memory of the first receiving channel; The clock output end of the second receiving channel is coupled with the clock circuit of the second receiving channel through the buffer memory of the second receiving channel.
4. 4. A transmission chip as claimed in any one of claims 1 to 3, wherein the first receive channel further comprises an equalisation input and the second receive channel further comprises an equalisation output; and the equalization input end of the first receiving channel is coupled with the equalization output end of the second receiving channel.
5. 5. The transmit chip of claim 4, wherein the first receive channel and the second receive channel each comprise an equalization circuit; The equalization input end of the first receiving channel is coupled with the equalization circuit of the first receiving channel, and the equalization output end of the second receiving channel is coupled with the equalization circuit of the second receiving channel.
6. 6. The transmit chip of claim 5, wherein the first receive channel and the second receive channel each comprise a buffer; The equalization input end of the first receiving channel is coupled with the equalization circuit of the first receiving channel through the buffer memory of the first receiving channel; and the equalization output end of the second receiving channel is coupled with the equalization circuit of the second receiving channel through the buffer memory of the second receiving channel.
7. 7. The transmission chip according to any one of claims 4 to 6, wherein, The transmission chip is used for responding to a starting instruction, controlling the first receiving channel to input equalization information from the equalization output end of the second receiving channel through the equalization input end of the first receiving channel.
8. 8. The transmission chip according to any one of claims 1 to 7, wherein, The transmission chip is used for responding to a starting instruction, controlling the first receiving channel to input clock information from the clock output end of the second receiving channel through the clock input end of the first receiving channel; wherein the clock information includes frequency information or the clock information includes frequency information and phase information.
9. 9. The transmission chip is characterized by comprising a plurality of receiving ends and a plurality of receiving channels, wherein the plurality of receiving channels comprise a first receiving channel, and the first receiving channel comprises a buffer; the plurality of receiving ends are coupled with the plurality of receiving channels in a one-to-one correspondence manner; The transmission chip is used for responding to a closing instruction and controlling the first receiving channel to store clock information into a cache of the first receiving channel; the transmission chip is further used for responding to a starting instruction and controlling the first receiving channel to read the clock information from the buffer memory of the first receiving channel; Wherein the clock information includes frequency information.
10. 10. The transmission chip of claim 9, wherein the transmission chip comprises a plurality of transmission chips, The transmission chip is further used for responding to the closing instruction and controlling the first receiving channel to store equalization information into a buffer memory of the first receiving channel; the transmission chip is further configured to control the first receiving channel to read the equalization information from the buffer memory of the first receiving channel in response to the start instruction.
11. 11. The transmission chip of claim 9 or 10, wherein the plurality of receiving channels further comprises a second receiving channel; The transmission chip is further configured to receive the closing instruction from a receiving end coupled to the first receiving channel or the second receiving channel.
12. 12. The transmission chip according to claim 9 or 10, wherein the transmission chip is configured to couple to a processor; the transmission chip is further used for receiving the closing instruction from the processor.
13. 13. The transmission chip of any one of claims 7-12, wherein the plurality of receive channels further comprises a second receive channel; The transmission chip is further configured to receive the start instruction from a receiving end correspondingly coupled to the second receiving channel.
14. 14. The transmission chip according to any one of claims 7-12, wherein the transmission chip is configured to couple to a processor; The transmission chip is further used for receiving the starting instruction from the processor.
15. 15. The transmission chip according to any one of claims 7 to 14, wherein, The transmission chip is further configured to receive data through the receiving end correspondingly coupled to the first receiving channel after receiving the start instruction.
16. 16. The transmission method is applied to a transmission chip, the transmission chip comprises a plurality of receiving ends and a plurality of receiving channels, the plurality of receiving channels comprise a first receiving channel and a second receiving channel, the first receiving channel comprises a clock input end, the second receiving channel comprises a clock output end, the plurality of receiving ends are coupled with the plurality of receiving channels in a one-to-one correspondence manner, the clock input end of the first receiving channel is coupled with the clock output end of the second receiving channel, and the transmission method comprises the following steps: receiving a starting instruction; in response to the start instruction, controlling the first receiving channel to input clock information from the clock output end of the second receiving channel through the clock input end of the first receiving channel; wherein the clock information includes frequency information or the clock information includes frequency information and phase information.
17. 17. The transmission method of claim 16, wherein the first receive channel further comprises an equalization input and the second receive channel further comprises an equalization output, wherein the equalization input of the first receive channel is coupled to the equalization output of the second receive channel, wherein the transmission method further comprises: And responding to the starting instruction, controlling the first receiving channel to input equalization information from the equalization output end of the second receiving channel through the equalization input end of the first receiving channel.
18. 18. The transmission method is applied to a transmission chip, the transmission chip comprises a plurality of receiving ends and a plurality of receiving channels, the plurality of receiving channels comprise a first receiving channel, the first receiving channel comprises a buffer memory, the plurality of receiving ends are coupled with the plurality of receiving channels in a one-to-one correspondence mode, and the transmission method comprises the following steps: receiving a closing instruction; Responding to the closing instruction, and controlling the first receiving channel to store clock information into a cache of the first receiving channel; receiving a starting instruction; Responding to the starting instruction, and controlling the first receiving channel to read the clock information from a cache of the first receiving channel; Wherein the clock information includes frequency information.
19. 19. The transmission method according to claim 18, characterized in that the transmission method further comprises: Controlling the first receiving channel to store equalization information into a buffer memory of the first receiving channel in response to the closing instruction; And responding to the starting instruction, and controlling the first receiving channel to read the equalization information from the buffer memory of the first receiving channel.
20. 20. The transmission method according to claim 18 or 19, wherein the plurality of reception channels further includes a second reception channel, and wherein the reception close instruction includes: And receiving the closing instruction from a receiving end correspondingly coupled with the first receiving channel or the second receiving channel.

Description

Transmission chip, transmission method, chip system, optical module and transmission device Technical Field The embodiment of the application relates to the technical field of chips, in particular to a transmission chip, a transmission method, a chip system, an optical module and a transmission device. Background The high-speed interconnect communication system may include a plurality of chips, and each chip may include a plurality of channels (transmit channels or receive channels) and a transmission port (transmit or receive) coupled to each channel. The channel is used for converting data into a form that can be transmitted or processed, and the transmission port is used for transmitting data. During data transmission, the data flow is sometimes larger, and the data flow is sometimes smaller. The chips can be made to dynamically open channels when data is transmitted by the chips. For example, when the data flow is large, the chips can open all channels so as to improve the interconnection bandwidth, and when the data flow is small, the chips can open part of channels and close the other part of channels so as to reduce the power consumption. Thus, the maximum dynamic energy saving benefit can be realized. When the flow rate is changed from small to large, some channels which are originally closed need to be restarted, and a plurality of chips transmit data through the restarted channels. In this process, the clock at which one chip sends data may not coincide with the clock at which the other chip receives the data. After receiving the data, the channel of the receiving side chip needs to be clock-synchronized with the channel of the transmitting side chip. But the time for the clocks of the channels to synchronize is longer, resulting in longer start-up times for the transmission channels in which the channels are located. Disclosure of Invention The embodiment of the application provides a transmission chip, a transmission method, a chip system, an optical module and a transmission device, which solve the problem of long starting time of a transmission channel in the prior art. In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme: In a first aspect, a transmission chip is provided, the transmission chip including a plurality of receiving terminals and a plurality of receiving channels, the plurality of receiving channels including a first receiving channel and a second receiving channel. The first receive channel includes a clock input and the second receive channel includes a clock output. The plurality of receiving ends are coupled with the plurality of receiving channels in a one-to-one correspondence manner. The clock input of the first receiving channel is coupled to the clock output of the second receiving channel. In the above technical solution, the clock input terminal of the first receiving channel is coupled to the clock output terminal of the second receiving channel. The first receiving channel may receive clock information of the second receiving channel via a clock input. The first receiving channel can directly receive clock information without processing data through a clock circuit to obtain the clock information. The clock information is obtained by processing the data by the clock circuit, and the time is longer than the time for directly receiving the clock information. The start-up time of this embodiment is therefore short. This embodiment may reduce the start-up time of the path in which the first receive channel is located from the 100 microsecond level to the nanosecond level. The service scene of microsecond-level message gaps can be reduced, and the requirement of a low-power-consumption interconnection function is met. In a possible implementation manner of the first aspect, the first receiving channel and the second receiving channel each include a clock circuit. The clock input of the first receive channel is coupled to the clock circuit of the first receive channel. The clock output of the second receive channel is coupled to the clock circuit of the second receive channel. In the above possible implementation manner, the clock circuit of the second receiving channel may output clock information to the clock circuit coupled to the clock input of the first receiving channel through the clock output of the second receiving channel. Thus, the circuit is simpler, and the transmission speed of clock information is faster. In a possible implementation manner of the first aspect, the first receiving channel and the second receiving channel each include a buffer. The clock input of the first receive channel is coupled to the clock circuit of the first receive channel through the buffer of the first receive channel. The clock output end of the second receiving channel is coupled with the clock circuit of the second receiving channel through the buffer memory of the second receiving channel. In the above possible implement