CN-122001839-A - Chip power consumption control method, device, chip, network interface card, apparatus, medium and program product

Abstract

The present application relates to a chip power consumption control method, apparatus, chip, network interface card, device, medium and program product. The method comprises the steps of obtaining network flow characteristics of at least one dimension of an acquired chip, generating a hardware resource activation strategy based on the network flow characteristics, wherein the hardware resource activation strategy comprises the steps of determining network flow processing hardware corresponding to the network flow characteristics, obtaining flow demand based on the network flow characteristics, obtaining activation quantity of the network flow processing hardware based on the flow demand, taking the activation quantity of the network flow processing hardware as the hardware resource activation strategy, and controlling power consumption of at least one network flow processing hardware of the chip based on the hardware resource activation strategy. The method can dynamically regulate and control the hardware resource and the power consumption state of the chip based on the real-time network flow characteristics.

Inventors

• SHI HONGBO
• BAO YALIN
• YAN BO

Assignees

• 深圳云豹智能股份有限公司

Dates

Publication Date

20260508

Application Date

20260408

Claims (17)

1. 1. A method for controlling power consumption of a chip, the method comprising: acquiring network flow characteristics of at least one dimension of the acquired chip; Generating a hardware resource activation policy based on the network traffic characteristics; And performing power consumption control on at least one network traffic processing hardware of the chip based on the hardware resource activation policy.
2. 2. The method of claim 1, wherein generating a hardware resource activation policy based on the network traffic characteristics comprises: Determining network traffic processing hardware corresponding to the network traffic characteristics; And obtaining a flow demand based on the network flow characteristics, and obtaining a hardware resource activation strategy corresponding to the network flow processing hardware based on the flow demand, wherein the hardware resource activation strategy comprises the activation quantity of the network flow processing hardware.
3. 3. The method of claim 2, wherein the network traffic characteristics include at least one of port traffic characteristics, interaction traffic characteristics of a source port and a destination port, traffic characteristics, and bursty traffic characteristics, and wherein the determining network traffic processing hardware corresponding to the network traffic characteristics comprises: And determining at least one of a port, a switching structure module, a packet processing unit and a cache module corresponding to the network traffic characteristics as network traffic processing hardware.
4. 4. The method according to claim 2, wherein the obtaining a traffic demand based on the network traffic feature and obtaining a hardware resource activation policy corresponding to the network traffic processing hardware based on the traffic demand comprises: Generating a traffic demand based on at least one of a port instantaneous bandwidth and a no-traffic duration, and obtaining at least one of a rate adjustment policy of a port physical layer and a medium access control layer of the chip and a hierarchical sleep policy of the port physical layer and the medium access control layer of the chip based on the traffic demand, in a case where the network traffic processing hardware includes a port; Generating a flow demand based on corresponding link bandwidth ratios of each source port and each destination port under the condition that the network flow processing hardware comprises a switch structure module, and generating a hardware resource activation strategy for closing an idle link and/or reducing clock frequency based on the flow demand, wherein the idle link is a link with the corresponding link bandwidth ratio of each source port and each destination port smaller than a first bandwidth ratio; In the case where the network traffic processing hardware includes a packet processing unit, generating a traffic demand based on at least one of traffic priority and packet processing complexity, and generating at least one of a hardware resource activation policy for traffic allocation and a hardware resource activation policy for traffic processing path based on the traffic demand; And under the condition that the network traffic processing hardware comprises a cache module, predicting cache demands in a future time period based on the traffic burst parameter to obtain traffic demand, and generating cache activation quantity based on the traffic demand to obtain a hardware resource activation strategy.
5. 5. The method of claim 4, wherein the network traffic processing hardware comprises ports; The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation policy includes: adjusting the rate of the port sending network traffic if the hardware resource activation policy includes a rate adjustment policy; And managing functional modules except a preamble detection module in the port physical layer and functional modules except a wake-up triggering module in the media access control layer under the condition that the hardware resource activation strategy comprises a hierarchical sleep strategy.
6. 6. The method of claim 4, wherein deriving the rate adjustment policy for the port physical layer and the medium access control layer of the chip based on the traffic demand comprises: generating a rate adjustment strategy of rate degradation of a port physical layer and a media access control layer of the chip under the condition that the port instantaneous bandwidth is continuously preset for a period of time which is lower than a first target threshold value; And under the condition that the instantaneous bandwidth of the port is continuously preset for a time period greater than or equal to a second target threshold, generating a rate adjustment strategy for rate upgrading of a port physical layer and a media access control layer of the chip, wherein the first target threshold is smaller than the second target threshold, and the first target threshold and the second target threshold are determined based on the current rate of the port.
7. 7. The method of claim 4, wherein the network traffic processing hardware comprises a switch fabric module; The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation policy includes: Under the condition that the hardware resource activation strategy comprises closing an idle link, closing a clock drive of the link through the switch structure module, and cutting off a power supply; In the case that the hardware resource activation policy includes reducing a clock frequency, reducing, by the switch fabric module, the clock frequency of the corresponding link; and storing the route information corresponding to the active link and carrying out invalid marking on the idle link under the condition that the hardware resource activation strategy comprises closing the idle link or reducing the clock frequency.
8. 8. The method of claim 4, wherein the network traffic processing hardware comprises a packet processing unit; The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation policy includes: In the case that the hardware resource activation policy includes a hardware resource activation policy of service allocation, processing services of different service priorities through different core groups of the chip; In the case that the hardware resource activation policy includes a hardware resource activation policy of a traffic processing path, traffic of different packet processing complexity is processed based on the traffic processing path.
9. 9. The method of claim 8, wherein the chip comprises a first core group and a second core group, wherein the generating a hardware resource activation policy for traffic allocation based on traffic demand comprises: Distributing the business of the first priority to a first core group for processing; Dynamically activating the second core group by clock gating in the presence of second priority traffic other than the first priority and assigning the second priority traffic to the second core group; and if the second priority service except the first priority service does not exist, the clock of the second core group is turned off.
10. 10. The method of claim 4, wherein the network traffic processing hardware comprises a cache module, and the cache module comprises a number of independently dormant memory blocks; The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation policy includes: And activating the corresponding storage blocks in the cache module according to the cache activation quantity.
11. 11. The method of claim 10, wherein the generating the cache activation quantity based on the traffic demand comprises: generating a cache activation number based on the cache demand and a first redundancy proportion; the activating the corresponding storage block in the cache module according to the cache activation number includes: and increasing the activation number when the actual cache occupancy in the cache module is greater than a target demand capacity, wherein the target demand capacity is determined based on the cache demand and a second redundancy proportion, and the second redundancy proportion is greater than the first redundancy proportion.
12. 12. A chip power consumption control apparatus, the apparatus comprising: The network flow characteristic acquisition module is used for acquiring network flow characteristics of at least one dimension of the acquired chip; The hardware resource activation policy generation module is used for generating a hardware resource activation policy based on the network traffic characteristics; And the low-power consumption module is used for controlling the power consumption of at least one network traffic processing hardware of the chip based on the hardware resource activation strategy.
13. 13. A chip comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 11 when the computer program is executed.
14. 14. A network interface card comprising a chip as claimed in claim 13 and a plurality of interfaces through which the chip processes data or communicates externally.
15. 15. A computer device comprising the network interface card of claim 14 for processing data or communicating externally.
16. 16. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 11.
17. 17. A computer program product comprising a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 11.

Description

Chip power consumption control method, device, chip, network interface card, apparatus, medium and program product Technical Field The present application relates to the field of network chip technologies, and in particular, to a method, an apparatus, a chip, a network interface card, a device, a medium, and a program product for controlling chip power consumption. Background With the development of chip technology, control of power consumption of a chip is particularly important. In the conventional technology, the power consumption of the chip can be controlled by a hardware static optimization technology and a dynamic adjustment technology. Wherein hardware static optimization techniques include process upgrades and low leakage transistor designs. The process is improved, the leakage current and the switching power consumption of the transistor are reduced (the power consumption is reduced by 30% -50% under the same calculation force) by adopting a more advanced process (such as from 14nm to 7nm/5 nm), the defects are that the cost is steeply increased, the static power consumption is increased instead, the low-leakage transistor is designed by adopting a High-threshold voltage (High-Vth) transistor, and the leakage current in idle is reduced (the static power consumption can be reduced by 40%). The switching speed of the transistor is reduced by 15% -20%, so that performance loss is caused in a high-frequency scene, flow change cannot be dynamically adapted, the transistor is required to be switched to a Low threshold voltage (Low-Vth) transistor in high load, switching delay is hundreds of nanoseconds, and burst flow cannot be adapted. Dynamic scaling techniques include traditional DVFS (dynamic voltage frequency scaling), clock Gating (Clock Gating), and port level sleep. Where conventional DVFS (dynamic voltage frequency scaling) adjusts voltage/frequency (e.g., from 1.0V/1GHz down to 0.8V/500 MHz) based on the overall load of the chip (e.g., PPU utilization). The method has the defects that based on global average load adjustment, adjustment lag (response time is more than or equal to 100 mu s) cannot cope with microsecond-level burst flow, and performance jitter (delay fluctuation is more than or equal to 50 mu s) is easy to cause. Clock Gating (Clock Gating) turns off Clock signals to idle modules (e.g., turns off PPU clocks when no packet is processed), reducing dynamic power consumption. The method has the defects that dynamic Power consumption can be restrained, static leakage Power consumption is ineffective (the optimization effect is limited in a scene with the proportion exceeding 50%), burr Power consumption exists when a clock is turned on/off, and extra Power consumption is increased by 10% -15% when frequent switching is performed. Port level sleep-the port enters a low power sleep mode (turns off part of PHY circuitry) when no traffic is flowing and wakes up when traffic is detected. The method has the defects that the dormancy/awakening period is long (more than or equal to 10 ms), and the method cannot adapt to microsecond-level burst traffic of a 5G base station and a data center (the awakening delay causes the first packet loss rate to be more than or equal to 1%). In summary, a low-power consumption scheme capable of dynamically regulating and controlling chip hardware resources and power consumption states based on real-time network traffic characteristics is urgently needed. Disclosure of Invention In view of the foregoing, it is desirable to provide a chip power consumption control method, apparatus, chip, network interface card, device, medium and program product capable of dynamically adjusting and controlling chip hardware resources and power consumption states based on real-time network traffic characteristics. In a first aspect, the present application provides a method for controlling power consumption of a chip, the method comprising: acquiring network flow characteristics of at least one dimension of the acquired chip; Generating a hardware resource activation policy based on the network traffic characteristics; And performing power consumption control on at least one network traffic processing hardware of the chip based on the hardware resource activation policy. In one embodiment, the generating a hardware resource activation policy based on the network traffic characteristics includes: Determining network traffic processing hardware corresponding to the network traffic characteristics; And obtaining a flow demand based on the network flow characteristics, and obtaining a hardware resource activation strategy corresponding to the network flow processing hardware based on the flow demand, wherein the hardware resource activation strategy comprises the activation quantity of the network flow processing hardware. In one embodiment, the network traffic characteristics include at least one of port traffic characteristics, interaction traffic characteristics of a source por