CN-122002151-A - Data reading method and reading circuit of image sensor memory array

Abstract

The invention provides a data reading method and a data reading circuit of an image sensor memory array, which are used for adjusting the voltage or the width or the phase of a reading enabling signal of each column according to the distance between each column in the memory array and a reading control unit so as to compensate the delay of the reading enabling signal generated in the decoding process, reduce the difference between the far end and the near end of the array on the premise of not increasing the area and the power consumption of a chip as much as possible, increase the effective reading time of the far end of the array and the discharge pressure difference and improve the working frequency under the condition of keeping the original reading frequency.

Inventors

• GUO FAN
• DONG XIAOYING

Assignees

• 格科微电子（上海）有限公司

Dates

Publication Date

20260508

Application Date

20241106

Claims (18)

1. 1. A method for reading data from an image sensor memory array, comprising: The decoder is used for providing a read-out enabling signal for each column in the storage array after decoding according to the address signals provided by the address control unit so that each column of data in the storage array is read out by the read-out control unit; and adjusting the voltage or width or phase of the readout enabling signals of each column according to the distance between each column in the storage array and the readout control unit so as to compensate the readout enabling signal delay generated in the decoding process.
2. 2. The method according to claim 1, wherein in the memory array, a side close to the readout control unit is an array near side, a side far from the readout control unit is an array far side, and the phase of the readout enable signal of each column is adjusted by the address control unit so that the discharge voltage difference of each column is substantially equal.
3. 3. The method of claim 2, wherein the address control unit samples the original address signal using sampling clock signals of different phases and outputs the sampled address signal to the decoder, and the sampling clock signal near the far end of the array is relatively advanced than the sampling clock signal near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.
4. 4. The method for reading data from an image sensor memory array according to claim 2, wherein the address control unit receives the original address signals of different phases, samples the original address signals, and outputs the sampled original address signals to the decoder, wherein the original address signals near the far end of the array are relatively earlier than the original address signals near the near end of the array, so that the phase of the read enable signals of each column is adjusted.
5. 5. The method for reading data from an image sensor memory array according to claim 2, wherein the sequence of reading data from each column in the memory array is sequentially, intermittently or randomly from the near end of the array to the far end of the array or from the far end of the array to the near end of the array.
6. 6. The method for reading out data of an image sensor memory array according to claim 3, The address control unit comprises an address sampling unit, an address driving unit, a logic control unit, a gating unit and at least one delay module; The address sampling unit samples an original address signal according to the sampling clock signal, the address driving unit drives the sampled address signal, and the address signal after driving is output to the decoder; The logic control unit divides the memory array into at least two sections according to at least one of an original address signal, a sampled address signal and a driven address signal, and outputs corresponding control signals respectively, and the gating unit selects an original sampling clock signal or a sampling clock signal delayed by the delay module according to the control signals and provides the sampling clock signal for the address sampling unit to sample.
7. 7. The method of claim 6, wherein the sampling clock signal near the far end of the array is the original clock signal, the sampling clock signal near the near end of the array is the delayed clock signal by the delay module, and the delay of the sampling clock signal near the near end of the array is greater.
8. 8. The method of claim 6, wherein the read control unit includes a clock control unit receiving an input clock signal and generating an operation enable signal of a differential amplifier, and the effective discharge time of the differential amplifier is controlled by the read enable signal of the decoder and the operation enable signal of the differential amplifier.
9. 9. The method of claim 8, wherein the input clock signal is the same clock signal as the original sampling clock signal.
10. 10. A data read-out circuit of an image sensor memory array is characterized in that, The device comprises an address control unit, a decoder, a memory array and a read-out control unit; The decoder is used for providing a read-out enabling signal for each column in the storage array after decoding according to the address signals provided by the address control unit so that each column of data in the storage array is read out by the read-out control unit; and adjusting the voltage or width or phase of the readout enabling signals of each column according to the distance between each column in the storage array and the readout control unit so as to compensate the readout enabling signal delay generated in the decoding process.
11. 11. The data readout circuit of the image sensor memory array according to claim 10, wherein in the memory array, an end close to the readout control unit is an array near end, an end far from the readout control unit is an array far end, and the phase of the readout enable signal of each column is adjusted by the address control unit so that the discharge voltage differences of each column are substantially equal.
12. 12. The data readout circuit of the image sensor memory array according to claim 11, wherein the address control unit samples the original address signal with sampling clock signals of different phases and outputs the sampled address signal to the decoder, and the sampling clock signal near the far end of the array is relatively advanced than the sampling clock signal near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.
13. 13. The data readout circuit of the image sensor memory array according to claim 11, wherein the address control unit receives the original address signals of different phases, samples the original address signals, outputs the sampled original address signals to the decoder, and the original address signals near the far end of the array are relatively advanced with respect to the original address signals near the near end of the array, thereby adjusting the phases of the readout enable signals of the columns.
14. 14. The data readout circuit of the image sensor memory array according to claim 11, wherein the data of each column in the memory array is sequentially read, intermittently read, or randomly read from the near end of the array to the far end of the array or from the far end of the array to the near end of the array.
15. 15. The data readout circuit of the image sensor memory array of claim 12, The address control unit comprises an address sampling unit, an address driving unit, a logic control unit, a gating unit and at least one delay module; The address sampling unit samples an original address signal according to the sampling clock signal, the address driving unit drives the sampled address signal, and the address signal after driving is output to the decoder; The logic control unit divides the memory array into at least two sections according to at least one of an original address signal, a sampled address signal and a driven address signal, and outputs corresponding control signals respectively, and the gating unit selects an original sampling clock signal or a sampling clock signal delayed by the delay module according to the control signals and provides the sampling clock signal for the address sampling unit to sample.
16. 16. The data readout circuit of the image sensor memory array of claim 15, wherein the sampling clock signal near the far end of the array is an original clock signal, the sampling clock signal near the near end of the array is a delayed clock signal by the delay module, and the delay of the sampling clock signal near the near end of the array is greater.
17. 17. The data read-out circuit of the image sensor memory array of claim 15, wherein the read-out control unit comprises a clock control unit and a differential amplifier, the clock control unit receiving an input clock signal and generating an operation enable signal of the differential amplifier, an effective discharge time of the differential amplifier being controlled by the read-out enable signal of the decoder and the operation enable signal of the differential amplifier.
18. 18. The data readout circuit of the image sensor memory array of claim 17, wherein the input clock signal is the same clock signal as the original sampling clock signal.

Description

Data reading method and reading circuit of image sensor memory array Technical Field The invention relates to a data reading method and a reading circuit of an image sensor memory array. Background Image sensors typically employ a memory array to store column data. When the storage data in the storage array is read out, the address decoder outputs a read-out enabling signal of each column by column according to an address change rule, the storage data of the selected column is usually discharged through a bit line and then read out through a sensitive amplifier of a read-out control unit, and the differential structure is adopted for reading out, so that the voltage difference of the actually needed discharge of the bit line can be effectively reduced, the power consumption is reduced, and the reading speed is improved. However, the read control unit is usually located at one side of the memory array, and the distance between each column of memory cells in the memory array and the read control unit must be far or near, and the function or timing of the read control unit is usually fixed, which results in that a single function or timing cannot meet the difference caused by different distances between each column in the memory array and the read control unit. For example, fig. 1 shows a Data readout circuit structure of a conventional image sensor memory array, which includes a decoder 102, a memory array 103 and a readout control unit 104, input address signals a < i:0> are transmitted to the decoder 102, the decoder 102 can generate a readout enable signal WL for each column according to switching of the address signals, the memory array 103 discharges the bit lines BL/BLb during readout, and as a result Data is generated in the readout control unit 104. The read control unit 104 includes a clock control unit 1041 and a differential amplifier 1042, as shown in fig. 2, where the clock control unit 1041 receives an input clock signal clk and generates an operation enable signal sen of the corresponding differential amplifier 1042, and the differential amplifier 1042 operates under control of the operation enable signal sen after discharging the bit line BL/BLb and outputs a final result Data. The BL/BLb discharging process needs to maintain a fixed timing relationship with the operation enable signal sen, so that the differential amplifier 1042 starts to operate when the discharging voltage difference of the bit line BL/BLb is maximum, which is advantageous in that the read data is not erroneous. However, as the size of the memory array 103 increases, the difference between the far and near ends of the array increases, in the embodiment shown in fig. 1, the readout control unit 104 is located at the left side of the memory array 103, the end close to the readout control unit 104 is the near end 103a of the array, the end far from the readout control unit 104 is the far end 103b of the array, and the far end 103b of the array delays due to the delay of the address signal a < i:0>, the readout enable signal WL is correspondingly delayed, so that the partial discharge time is wasted, the discharge pressure difference decreases, and as the requirement of the chip on the readout frequency increases gradually, the effective readout time of the data further shortens, the bit line discharge pressure difference during the readout decreases, and the working frequency is limited. In the prior art, the signal delay is reduced and the working frequency is improved mainly through schemes of reducing the array length (such as block driving, reducing the length of each block), reducing the resistance of a signal line (widening wiring), increasing the discharge speed (increasing the size of a discharge tube), and the like, but the schemes have certain defects such as increasing the area of a chip, increasing the power consumption, or bringing complex structural design, and the like. Therefore, a method and a circuit for improving the data readout performance of the memory array of the image sensor are needed, and on the premise of not increasing the area and the power consumption of a chip as much as possible, the signal delay caused by the difference between the far end and the near end of the array is reduced, the effective readout time of the far end of the array is increased, the discharge pressure difference is increased, and the working frequency is improved. Disclosure of Invention The invention aims to provide a data reading method and a data reading circuit for an image sensor memory array, which can reduce signal delay caused by the difference between the far end and the near end of the array, increase effective reading time of the far end of the array, increase discharge pressure difference and improve working frequency under the condition of keeping the original reading frequency. In order to solve the technical problems, one aspect of the invention provides a data reading method of an image sensor memory array,