CN-122002778-A - Static random access memory structure and manufacturing method thereof

Abstract

The invention discloses a static random access memory structure and a manufacturing method thereof, wherein the static random access memory structure comprises a silicon substrate, a shallow trench isolation arranged on the silicon substrate, a first fin structure connected with the silicon substrate and protruding out of the shallow trench isolation, a first grid structure crossing the first fin structure and part of the shallow trench isolation, so that the first grid structure covers a top surface and part of side walls of the first fin structure and forms a transmission gate transistor (PG) of the static random access memory, and a protruding part arranged under the first grid structure and on the shallow trench isolation, wherein the protruding part covers part of the surface of at least one side wall of the first fin structure, and the top surface of the protruding part is higher than the top surface of the shallow trench isolation.

Inventors

• HUANG JUNXIAN
• CHEN JIANHONG
• GUO YOUCE
• WANG SHURU
• ZENG JUNYAN

Assignees

• 联华电子股份有限公司

Dates

Publication Date

20260508

Application Date

20241120

Priority Date

20241106

Claims (20)

1. 1. A static random access memory structure comprising: A silicon substrate; shallow trench isolation on the silicon substrate; a first fin structure connected to the silicon substrate and protruding the shallow trench isolation; a first gate structure crossing the first fin structure and part of the shallow trench isolation to cover the top surface and part of the side wall of the first fin structure and form a pass gate transistor (PG) of the SRAM, and And a protrusion portion located directly under the first gate structure and on the shallow trench isolation, wherein the protrusion portion covers a portion of a surface of at least one side wall of the first fin structure, a top surface of the protrusion portion is higher than a top surface of the shallow trench isolation, a height in a vertical direction from the top surface of the shallow trench isolation to the top surface of the first fin structure is defined as h1, and a height in the vertical direction from the top surface of the shallow trench isolation to the top surface of the protrusion portion is defined as h2.
2. 2. The sram structure of claim 1, wherein the protrusion covers a portion of a surface of both sidewalls of the first fin structure in cross-section, wherein the top width of the first fin structure is defined as w1, and the first gate structure covers the first fin structure to form an effective channel width w1+2 (h 1-h 2) of the pass gate transistor.
3. 3. The sram structure of claim 1, wherein the protrusion covers only a portion of a surface of a single side wall of the first fin structure in cross-section, wherein the top width of the first fin structure is defined as w1, and the first gate structure covers the first fin structure to form an effective channel width w1+2h1-h2 of the pass gate transistor.
4. 4. The sram structure of claim 1, further comprising: a second fin structure connected to the silicon substrate and protruding the shallow trench isolation; And a second gate structure crossing the second fin structure and part of the shallow trench isolation, so that the second gate structure covers the top surface and part of the side wall of the second fin structure and forms a pull-down transistor (PD) of the static random access memory.
5. 5. The sram structure of claim 4, wherein the protrusion is not included between the bottom of the second gate structure and the shallow trench isolation of the pull-down transistor, wherein the top surface of the first fin structure and the top surface of the second fin structure are horizontally aligned with each other, and the bottom surface of the first fin structure and the bottom surface of the second fin structure are horizontally aligned with each other.
6. 6. The sram structure of claim 5, wherein the top width of the second fin structure is defined as w1, the height in the vertical direction from the top surface of the shallow trench isolation to the top surface of the second fin structure is defined as h1, and the effective channel width of the second gate structure covering the second fin structure to form the pull-down transistor is w1+2h1.
7. 7. The sram structure of claim 1, wherein a condition of 0< h2/h1<0.5 is satisfied.
8. 8. The structure of claim 1, wherein the material of the protrusion is different from the material of the shallow trench isolation.
9. 9. The structure of claim 1, wherein the material of the protrusion is the same as that of the shallow trench isolation, and the protrusion and the shallow trench isolation are integrally formed.
10. 10. A method for fabricating a sram structure, comprising: providing a silicon substrate; Forming shallow trench isolation on the silicon substrate; forming a first fin structure connected with the silicon substrate and protruding out of the shallow trench isolation; forming a first gate structure across the first fin structure and a portion of the shallow trench isolation such that the first gate structure covers a top surface and a portion of a sidewall of the first fin structure and forms a pass gate transistor (PG) of the SRAM, and Forming a protruding portion, located right below the first gate structure and located on the shallow trench isolation, wherein the protruding portion covers a part of a surface of at least one side wall of the first fin structure, a top surface of the protruding portion is higher than a top surface of the shallow trench isolation, a height from the top surface of the shallow trench isolation to the top surface of the first fin structure in a vertical direction is defined as h1, and a height from the top surface of the shallow trench isolation to the top surface of the protruding portion in the vertical direction is defined as h2.
11. 11. The method of claim 10, wherein the protrusion covers a portion of a surface of two sidewalls of the first fin structure when viewed in cross-section, wherein the top width of the first fin structure is defined as w1, and the first gate structure covers the first fin structure to form an effective channel width w1+2 (h 1-h 2) of the pass gate transistor.
12. 12. The method of claim 10, wherein the protrusion covers only a portion of a surface of a single side wall of the first fin structure when viewed in cross-section, wherein the width of the top surface of the first fin structure is defined as w1, and the effective channel width of the first gate structure covering the first fin structure to form the pass gate transistor is w1+2h1-h2.
13. 13. The static random access memory of claim 10a method for fabricating an access memory structure, the device also comprises: forming a second fin structure connected with the silicon substrate and protruding out of the shallow trench isolation; Forming a second gate structure, crossing the second fin structure and part of the shallow trench isolation, so that the second gate structure covers the top surface and part of the side wall of the second fin structure and forms a pull-down transistor (PD) of the static random access memory.
14. 14. The method of claim 13, wherein the protrusion is not included between the bottom of the second gate structure and the shallow trench isolation of the pull-down transistor, wherein the top surface of the first fin structure and the top surface of the second fin structure are aligned with each other in a horizontal direction, and the bottom surface of the first fin structure and the bottom surface of the second fin structure are aligned with each other in the horizontal direction.
15. 15. The method of claim 14, wherein a width of the top surface of the second fin structure is defined as w1, a height in the vertical direction from the top surface of the shallow trench isolation to the top surface of the second fin structure is defined as h1, and an effective channel width of the pull-down transistor formed by the second gate structure covering the second fin structure is w1+2h1.
16. 16. The method of claim 10, wherein 0< h2/h1<0.5 is satisfied.
17. 17. The method of claim 10, wherein the protruding portion is made of a material different from the material of the shallow trench isolation.
18. 18. The method of claim 17, wherein the forming the protrusion comprises: Forming a material layer on the shallow trench isolation after the shallow trench isolation is formed; A patterning step is performed to remove a portion of the material layer, and the remaining material layer is defined as the protrusion.
19. 19. The method of claim 10, wherein the protruding portion is made of the same material as the shallow trench isolation, and the protruding portion and the shallow trench isolation are integrally formed.
20. 20. The method of claim 19, wherein the forming the protrusion comprises: forming a mask layer on the shallow trench isolation after the shallow trench isolation is formed; A patterning step is performed to remove a portion of the shallow trench isolation not covered by the mask layer, and define the portion of the shallow trench isolation covered by the mask layer as the protrusion.

Description

Static random access memory structure and manufacturing method thereof Technical Field The present invention relates to a static random access memory (static random access memory, SRAM), and more particularly, to a layout pattern of a Static Random Access Memory (SRAM) with high performance and a method for fabricating the same. Background An embedded SRAM (embedded static random access memory) includes logic circuits (logic circuits) and SRAM connected to the logic circuits. The sram itself is a volatile memory cell (memory cell), i.e., the stored data is erased at the same time after the power supplied to the sram is lost. The static random access memory is designed by using the conductive state of the transistors in the memory cells, and is based on the mutual coupling transistors, so that the problem of discharging the capacitor is avoided, and the continuous charging is not needed to keep the data from losing, namely, the action of updating the memory is not needed, which is different from the mode of using the charged state of the capacitor to store the data in the dynamic random access memory (Dynamic Random Access Memory, DRAM) belonging to the same volatile memory. Static random access memory has a relatively high access speed, and is therefore used as a cache memory (cache memory) in a computer system. Disclosure of Invention The invention provides a static random access memory structure, which comprises a silicon substrate, a shallow trench isolation arranged on the silicon substrate, a first fin structure connected with the silicon substrate and protruding out of the shallow trench isolation, a first grid structure crossing the first fin structure and part of the shallow trench isolation, wherein the first grid structure covers a top surface and part of side walls of the first fin structure and forms a transmission gate transistor (PG) of the static random access memory, and a bulge arranged right below the first grid structure and on the shallow trench isolation, wherein the bulge covers part of the surface of at least one side wall of the first fin structure, the top surface of the bulge is higher than the top surface of the shallow trench isolation, the height from the top surface of the shallow trench isolation to the top surface of the first fin structure in a vertical direction is defined as h1, and the height from the top surface of the shallow trench isolation to the top surface of the bulge in the vertical direction is defined as h2. The invention also provides a method for fabricating a static random access memory structure, comprising providing a silicon substrate, forming a shallow trench isolation on the silicon substrate, forming a first fin structure connected to the silicon substrate and protruding the shallow trench isolation, forming a first gate structure crossing the first fin structure and part of the shallow trench isolation, so that the first gate structure covers a top surface and part of a sidewall of the first fin structure and forms a pass gate transistor (PG) of the static random access memory, and forming a protrusion part under the first gate structure and on the shallow trench isolation, wherein a top surface of the protrusion part covers a part of a sidewall of at least one side of the first fin structure, the top surface of the protrusion part is higher than a top surface of the shallow trench isolation, a height from the top surface of the shallow trench isolation to the top surface of the first fin structure in a vertical direction is defined as h1, and a height from the top surface of the shallow trench isolation to the top surface of the protrusion part in the vertical direction is defined as h2. The invention is characterized in that in order to improve the element quality, the ratio of the on-current of the PD transistor to the on-current of the PG transistor is improved, but the width of the fin structure formed by the sidewall pattern transfer mode cannot be adjusted only by the photomask pattern. Therefore, the invention adjusts the channel width of the transistor by changing the shallow trench isolation or the protrusion height around the fin structure. More specifically, the invention uses etching process to cut shallow trench isolation beside other transistors except PG transistor, or uses another mask layer to cover beside PG fin structure, so that when grid structure is covered on fin structure, channel width of PD transistor is larger than channel width of PG transistor, further reducing turn-on current of PG transistor, achieving purpose of raising beta value and static noise margin of SRAM. Drawings For a better understanding of the present invention, reference should be made to the drawings and to the detailed description thereof when read in light of the accompanying drawings. Specific embodiments of the present invention will be described in detail herein with reference to the accompanying drawings and to illustrate the principles of the inven