CN-122002779-A - Semiconductor structure, manufacturing method thereof, memory and memory system

Abstract

Embodiments of the present disclosure provide a semiconductor structure, a method of manufacturing the same, a memory, and a memory system. The semiconductor structure comprises a memory array and a second subarray, wherein the memory array comprises a first subarray and a second subarray, the first subarray comprises first semiconductor columns which extend along a first direction and are arranged at intervals along a second direction and a third direction, the second subarray comprises second semiconductor columns which extend along the first direction and are arranged at intervals along the second direction and the third direction, a first end part of the first semiconductor columns which are arranged along the second direction in the first subarray and a second end part of the second semiconductor columns which are arranged along the second direction in the second subarray in the same memory array are coupled to the same bit line, and any two of the first direction, the second direction and the third direction are intersected.

Inventors

• LIU ZICHEN
• LIU WEI
• HUO ZONGLIANG

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260508

Application Date

20241029

Claims (20)

1. 1. The semiconductor structure comprises a memory array, a first storage layer, a second storage layer and a first storage layer, wherein the memory array comprises a first subarray and a second subarray; the first subarray comprises first semiconductor columns extending along a first direction and arranged at intervals along a second direction and a third direction; the second subarray comprises second semiconductor columns extending along the first direction and arranged at intervals along the second direction and the third direction; In the same memory array, a first end of a first semiconductor pillar arranged along the second direction in the first subarray and a second end of a second semiconductor pillar arranged along the second direction in the second subarray are coupled to the same bit line, wherein any two of the first direction, the second direction and the third direction intersect.
2. 2. The semiconductor structure of claim 1, wherein the first semiconductor pillar includes the first and third oppositely disposed ends along the first direction; the second semiconductor pillar includes the second end and a fourth end disposed opposite to each other along the first direction; in the same memory array, the first subarray and the second subarray are arranged along the first direction, and the distance between the first end part and the second end part in the first semiconductor column and the second semiconductor column arranged along the first direction is smaller than the distance between the third end part and the fourth end part.
3. 3. The semiconductor structure of claim 2, wherein in the same memory array, the bit lines extend along the second direction and are spaced apart along the third direction; The first end and the second end are mirror symmetric about the bit line, and the third end and the fourth end are mirror symmetric about the bit line.
4. 4. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: The first grid structure of the first semiconductor column arranged along the third direction is coupled to the same first word line, and the first word line extends along the third direction and is arranged at intervals along the second direction; The second grid structure of the second semiconductor column arranged along the third direction is coupled to the same second word line, and the second word line extends along the third direction and is arranged at intervals along the second direction.
5. 5. The semiconductor structure of claim 4, wherein a plurality of said memory arrays are arranged along said first direction to form a memory block, said semiconductor structure further comprising: A first conductive line to which the first word lines in different ones of the memory arrays in a same one of the memory blocks are coupled; and a second conductive line to which the second word lines in different memory arrays in the same memory block are coupled.
6. 6. The semiconductor structure of claim 5, wherein the number of first conductive lines in the same memory block is the same as the number of first semiconductor pillars arranged in the second direction in each of the first subarrays; The number of the second conductive lines in the same memory block is the same as the number of the second semiconductor pillars arranged in the second direction in each of the second sub-arrays.
7. 7. The semiconductor structure of claim 5, wherein the semiconductor structure further comprises: A first connection portion provided between the first conductive line and the first word line, one end of the first connection portion being coupled to the first word line and the other end of the first connection portion being coupled to the first conductive line; And a second connection part arranged between the second conductive wire and the second word line, wherein one end of the second connection part is coupled to the second word line and the other end of the second connection part is coupled to the second conductive wire.
8. 8. The semiconductor structure of claim 5, wherein the first conductive lines and the second conductive lines each extend in the first direction, and the first conductive lines and the second conductive lines are alternately arranged in the second direction.
9. 9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises: The first conductive part is arranged on one side of the first conductive wire far away from the first semiconductor column and is coupled to the first conductive wire; the second conductive part is arranged on one side of the second conductive wire far away from the second semiconductor column and is coupled to the second conductive wire.
10. 10. The semiconductor structure of claim 9, wherein the first conductive line and the second conductive line are aligned in the second direction, the first conductive portion and the second conductive portion are each disposed on a same side of the memory block in the first direction, and the first conductive portion and the second conductive portion are offset in the second direction.
11. 11. The semiconductor structure of claim 9, wherein the first conductive line and the second conductive line are aligned in the second direction, the first conductive portion and the second conductive portion are each disposed on a same side of the memory block in the first direction, and the first conductive portion and the second conductive portion are aligned in the second direction.
12. 12. The semiconductor structure of claim 9, wherein the first conductive line and the second conductive line are offset in the second direction, the first conductive portion and the second conductive portion are each disposed on a same side of the memory block in the first direction, and the first conductive portion and the second conductive portion are offset in the second direction.
13. 13. The semiconductor structure of claim 9, wherein the first conductive line and the second conductive line are offset in the second direction, the first conductive portion and the second conductive portion are each disposed on different sides of the memory block in the first direction.
14. 14. The semiconductor structure of claim 2, wherein the semiconductor structure further comprises: The first capacitor is arranged on one side of the first semiconductor column close to the third end part and is coupled to the third end part; and the second capacitor is arranged on one side of the second semiconductor column close to the fourth end part and is coupled to the fourth end part.
15. 15. A memory, the memory comprising: the semiconductor structure of any one of claims 1 to 14, and Peripheral circuitry coupled to the semiconductor structure.
16. 16. The memory of claim 15, wherein the memory comprises a three-dimensional dynamic random access memory, 3D DRAM.
17. 17. A memory system, the memory system comprising: The memory according to claim 15 or 16, and A controller coupled to the memory and configured to control the memory.
18. 18. A method of fabricating a semiconductor structure, the method comprising: Forming a memory array, wherein the memory array comprises a first subarray and a second subarray, the first subarray comprises first semiconductor columns which extend along a first direction and are arranged at intervals along a second direction and a third direction, and the second subarray comprises second semiconductor columns which extend along the first direction and are arranged at intervals along the second direction and the third direction; And in the same storage array, a first end of a first semiconductor pillar arranged along the second direction in the first subarray and a second end of a second semiconductor pillar arranged along the second direction in the second subarray are coupled to the same bit line, wherein any two of the first direction, the second direction and the third direction intersect.
19. 19. The method of manufacturing of claim 18, wherein prior to forming a bit line between the first sub-array and the second sub-array, the method further comprises: The first grid structures of the first semiconductor columns arranged along the third direction are coupled to the same first word line, and the first word lines extend along the third direction and are arranged at intervals along the second direction; and the second grid structures of the second semiconductor columns arranged along the third direction are coupled to the same second word line, and the second word lines extend along the third direction and are arranged at intervals along the second direction.
20. 20. The method of manufacturing of claim 19, wherein the first semiconductor pillar includes the first and third ends disposed opposite each other along the first direction, the second semiconductor pillar includes the second and fourth ends disposed opposite each other along the first direction, the forming a bit line between the first and second subarrays, comprising: forming a bit line recess between a first end of the first semiconductor pillar and a second end of the second semiconductor pillar; And filling conductive materials in the bit line grooves to form bit lines, wherein the bit lines extend along the second direction and are distributed at intervals along the third direction in the same storage array.

Description

Semiconductor structure, manufacturing method thereof, memory and memory system Technical Field Embodiments of the present disclosure relate to the field of semiconductor technology, including but not limited to a semiconductor structure and a method of manufacturing the same, a memory, and a memory system. Background Dynamic random access memory (Dynamic Random Access Memory, DRAM) includes a plurality of memory cells, each memory cell typically including a transistor and a capacitor. The gate of the transistor is coupled to the word line, the source (or drain) of the transistor is coupled to the bit line, and the drain (or source) of the transistor is coupled to the capacitor. With the continuous miniaturization of DRAM structures, spatial expansion of DRAM is performed using three-dimensional structures to form three-dimensional DRAM (3D DRAM). Disclosure of Invention In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, a memory, and a memory system. In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows: In a first aspect, an embodiment of the disclosure provides a semiconductor structure, which comprises a memory array, wherein the memory array comprises a first subarray and a second subarray, the first subarray comprises first semiconductor columns which extend along a first direction and are arranged at intervals along a second direction and a third direction, the second subarray comprises second semiconductor columns which extend along the first direction and are arranged at intervals along the second direction and the third direction, and in the same memory array, first ends of the first semiconductor columns which are arranged along the second direction in the first subarray and second ends of the second semiconductor columns which are arranged along the second direction in the second subarray are coupled to the same bit line, wherein any two of the first direction, the second direction and the third direction intersect. In some embodiments, the first semiconductor pillars include the first and third ends disposed opposite each other along the first direction, the second semiconductor pillars include the second and fourth ends disposed opposite each other along the first direction, and the first and second sub-arrays are arranged along the first direction in the same memory array, wherein a distance between the first and second ends of the first and second semiconductor pillars arranged along the first direction is smaller than a distance between the third and fourth ends. In some embodiments, the bit lines extend in the second direction and are spaced apart in the third direction in the same memory array, the first and second ends are mirror symmetrical about the bit lines, and the third and fourth ends are mirror symmetrical about the bit lines. In some embodiments, the semiconductor structure further comprises a first gate structure arranged on at least one side wall of the first semiconductor column, the first gate structures of the first semiconductor column arranged along the third direction are coupled to the same first word line, the first word line extends along the third direction and is arranged at intervals along the second direction, a second gate structure arranged on at least one side wall of the second semiconductor column, the second gate structures of the second semiconductor column arranged along the third direction are coupled to the same second word line, and the second word line extends along the third direction and is arranged at intervals along the second direction. In some embodiments, the plurality of memory arrays are arranged along the first direction to form a memory block, and the semiconductor structure further includes a first conductive line to which the first word lines of different memory arrays in the same memory block are coupled, and a second conductive line to which the second word lines of different memory arrays in the same memory block are coupled. In some embodiments, the number of the first conductive lines in the same memory block and the number of the first semiconductor pillars arranged in the second direction in each of the first subarrays are the same, and the number of the second conductive lines in the same memory block and the number of the second semiconductor pillars arranged in the second direction in each of the second subarrays are the same. In some embodiments, the semiconductor structure further includes a first connection portion disposed between the first conductive line and the first word line, one end of the first connection portion being coupled to the first word line and the other end of the first connection portion being coupled to the first conductive line, and a second connection portion disposed between the second conductive line and the second word line, one end of the second connection portion bei