CN-122002780-A - Semiconductor structure, preparation method thereof and storage system

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips. The semiconductor structure includes a plurality of memory structures, a plurality of extraction layers, and a plurality of connection portions. The memory structure includes a capacitor unit and a first transistor structure stacked in a first direction perpendicular to the stacking direction. The plurality of memory structures are arranged in layers along a second direction and are arranged in columns along a stacking direction, wherein the second direction passes through a plane in which the stacking direction and the first direction are located. And a plurality of extraction layers are arranged at intervals along the stacking direction, and each extraction layer is connected with the grid electrode of each first transistor structure of the same layer. The connection portions extend in the stacking direction, and one connection portion is connected to one lead-out layer. The plurality of connecting parts are positioned on one side of the plurality of storage structures in the second direction, and the plurality of connecting parts are arranged at intervals along the first direction. The semiconductor structure is applied to the dynamic random access memory to realize the reading and writing of data.

Inventors

• DU XIAOLONG
• OuYang Lujia
• ZHOU WENXI
• XIA ZHILIANG
• HUO ZONGLIANG

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260508

Application Date

20241031

Claims (20)

1. 1. A semiconductor structure, comprising: The memory device comprises a plurality of memory structures, a plurality of memory modules and a plurality of memory modules, wherein the memory structures comprise capacitor units and first transistor structures which are stacked along a first direction perpendicular to a stacking direction; the extraction layers are positioned on at least one side of the capacitor units in the second direction, each extraction layer is connected with the grid electrode of each first transistor structure of the same layer, and the extraction layers are arranged at intervals along the stacking direction; The plurality of connecting parts are positioned at one side of the plurality of storage structures in the second direction, and the plurality of connecting parts are arranged at intervals along the first direction.
2. 2. The semiconductor structure of claim 1, wherein, The first transistor structure comprises a channel layer and a gate dielectric layer, the gate dielectric layer is positioned between the channel layer and the gate, the gate of the first transistor structure comprises a first gate and a second gate, the first gate is positioned on one side of the channel layer in the stacking direction, and the second gate is positioned on the other side of the channel layer in the stacking direction; The extraction layer comprises a first conductive layer and a second conductive layer, wherein the first conductive layer is connected with a first grid electrode of the first transistor structure, and the second conductive layer is connected with a second grid electrode of the first transistor structure.
3. 3. The semiconductor structure of claim 2, wherein, The connecting part comprises a first connecting part and a second connecting part, wherein the first connecting part is positioned between the first conductive layer and the second conductive layer, the first connecting part is connected with the first conductive layer and the second conductive layer, the second connecting part is positioned at one side of the first connecting part in the stacking direction, and the second connecting part extends along the stacking direction and is connected with the first connecting part.
4. 4. The semiconductor structure of claim 2, wherein, The connecting portion includes a third connecting portion extending in the stacking direction and connected to the first conductive layer, and a fourth connecting portion extending in the stacking direction and connected to the second conductive layer.
5. 5. The semiconductor structure of claim 4, wherein, The first conductive layer is arranged on the same layer as the first grid electrode of the first transistor structure, and the second conductive layer is arranged on the same layer as the second grid electrode of the first transistor structure.
6. 6. The semiconductor structure of claim 5, wherein, The third connecting part is positioned at one side of the first conductive layer, which is away from the second conductive layer, and the boundary of the third connecting part, which is close to one end of the first conductive layer, is positioned at the inner side of the boundary of the third connecting part, which is away from one end of the first conductive layer; the fourth connecting portion is located on one side, away from the first conductive layer, of the second conductive layer, and the boundary, close to one end of the second conductive layer, of the fourth connecting portion is located on the inner side, away from one end of the second conductive layer, of the fourth connecting portion.
7. 7. The semiconductor structure of claim 6, wherein, The third connecting portion and at least part of the fourth connecting portion are disposed opposite to each other in the stacking direction.
8. 8. The semiconductor structure of any of claims 2-7, wherein, The extraction layer further comprises an isolation layer, and the isolation layer is located between the first conductive layer and the second conductive layer.
9. 9. The semiconductor structure of claim 8, wherein, The memory structure further comprises a second transistor structure, wherein the second transistor structure is positioned on one side of the capacitor unit, which is away from the first transistor structure; The capacitor unit comprises a first inner electrode, a second inner electrode, a first outer electrode, a second outer electrode, a common electrode and a dielectric layer, wherein the first inner electrode and the second inner electrode are arranged at intervals along the first direction, the first inner electrode is closer to the first transistor structure than the second inner electrode, the first inner electrode is connected with the first transistor structure, the second inner electrode is connected with the second transistor structure, the first outer electrode surrounds the first inner electrode, the second outer electrode surrounds the second inner electrode, the common electrode is located between the first inner electrode and the second inner electrode and connected with the first outer electrode and the second outer electrode, the dielectric layer is located between the first inner electrode and the first outer electrode and between the second inner electrode and the second outer electrode, and the common electrode of the storage structures is connected into an integral structure.
10. 10. The semiconductor structure of claim 9, wherein the semiconductor structure comprises a silicon nitride layer, The extraction layer is connected with the grid electrode of each second transistor structure of the same layer.
11. 11. The semiconductor structure of claim 8, wherein, The material of the channel layer includes indium gallium zinc oxide, and the dimension of the channel layer in the stacking direction is greater than or equal to 2nm and less than or equal to 10nm.
12. 12. The semiconductor structure of claim 11, wherein, The channel layer extends in the first direction, and a dimension of the channel layer in the second direction increases and decreases in the first direction.
13. 13. The semiconductor structure of claim 8, wherein, The memory structure further includes a first insulating portion between the first external electrode and the gate electrode of the first transistor structure, and a second insulating portion between the second external electrode and the gate electrode of the second transistor structure.
14. 14. The semiconductor structure of claim 8, further comprising a plurality of first bit lines and a plurality of second bit lines; the first bit line is positioned on one side of the first transistor structure, which is away from the first internal electrode, extends along the stacking direction, is connected with a row of channel layers of the first transistor structure, and is arranged at intervals along the second direction; The second bit line is located at one side of the second transistor structure, which is away from the second internal electrode, extends along the stacking direction, is connected with a row of channel layers of the second transistor structure, and is arranged at intervals along the second direction.
15. 15. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises: A third insulating part located at one side of the common electrode in the first direction and located between the first internal electrodes of two adjacent columns of the memory structure; a fourth insulating portion located at a side of the third insulating portion facing away from the common electrode, and located at least one side of the first bit line in the second direction; A fifth insulating part located at the other side of the common electrode in the first direction and between the second internal electrodes of two adjacent columns of the memory structures; A sixth insulating portion located at a side of the fifth insulating portion facing away from the common electrode, and located at least one side of the second bit line in the second direction; and a seventh insulating part, wherein the seventh insulating part is positioned at two sides of the capacitor units of the storage structures in the second direction.
16. 16. The semiconductor structure of any one of claims 9-15, wherein the semiconductor structure further comprises: the storage structure, the extraction layer, the third insulation part, the fourth insulation part, the fifth insulation part, the sixth insulation part and the seventh insulation part are all embedded in the insulation layer.
17. 17. The semiconductor structure of claim 16, wherein, The third insulating part and the fourth insulating part extend along the stacking direction, and each comprise a first sub insulating part and a second sub insulating part which are alternately stacked along the stacking direction, wherein the size of the first sub insulating part in the direction perpendicular to the stacking direction is larger than the size of the second sub insulating part in the direction perpendicular to the stacking direction; The first transistor structure comprises a first insulating part, a second insulating part, a third insulating part, a fourth insulating part, a channel layer, a first insulating layer, a second insulating layer, a first transistor structure, a second transistor structure, a third transistor structure, a fourth transistor structure, a first transistor structure, a second transistor structure and a third transistor structure.
18. 18. A method of fabricating a semiconductor structure, comprising: forming a plurality of capacitor units, wherein the plurality of capacitor units are arranged in layers along a second direction and are arranged in columns along a stacking direction; Forming a plurality of extraction layers, wherein the extraction layers are positioned on at least one side of the plurality of capacitor units in the second direction, and the plurality of extraction layers are arranged at intervals along the stacking direction; Forming a first transistor structure stacked on one side of the capacitor unit along a first direction to form a memory structure, wherein each extraction layer is connected with a grid electrode of each first transistor structure of the same layer; And forming a plurality of connecting parts, wherein the connecting parts extend along the stacking direction, one connecting part is connected with one lead-out layer, the plurality of connecting parts are positioned at one side of the storage structure in the second direction, and the plurality of connecting parts are arranged at intervals along the first direction.
19. 19. The method of manufacturing according to claim 18, wherein the forming the connection portion includes: forming a first groove extending into the first conductive layer in the stacking direction; Reaming one end, close to the first conductive layer, of the first groove through the first groove to form a second groove, wherein the second groove exposes the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer form the extraction layer; The connecting portion is formed in the second groove.
20. 20. The method of manufacturing according to claim 18, wherein the forming the connection portion includes: forming two third grooves which extend along the stacking direction and expose the first conductive layer; removing part of the first conductive layer through one third groove to form a fourth groove, wherein the fourth groove exposes the second conductive layer, and the first conductive layer and the second conductive layer form the extraction layer; Forming a third connecting part in the third groove; and forming a fourth connecting part in the fourth groove, wherein the third connecting part and the fourth connecting part form the connecting part.

Description

Semiconductor structure, preparation method thereof and storage system Technical Field The disclosure relates to the technical field of semiconductor chips, and in particular relates to a semiconductor structure, a preparation method thereof and a storage system. Background Dynamic random access memory (dynamic random access memory, DRAM) is scaled to smaller sizes as process technology, circuit design, and manufacturing processes improve. However, as the feature size of memory cells within a memory approaches a lower limit, planar processing and fabrication techniques become challenging and costly, resulting in densities of memory cells approaching an upper limit. Therefore, how to further realize the miniaturization of the DRAM becomes a technical problem that is difficult for the current technicians to solve. Disclosure of Invention Embodiments of the present disclosure provide a semiconductor structure, a method of manufacturing the same, and a memory system. The embodiment of the disclosure adopts the following technical scheme: In one aspect, embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a plurality of memory structures, a plurality of extraction layers, and a plurality of connection portions. The memory structure includes a capacitor unit and a first transistor structure stacked in a first direction perpendicular to the stacking direction. The plurality of memory structures are arranged in layers along the second direction and in columns along the stacking direction. Wherein the second direction passes through a plane in which the lamination direction and the first direction lie. The extraction layers are arranged on at least one side of the plurality of capacitor units in the second direction, each extraction layer is connected with the grid electrode of each first transistor structure of the same layer, and the plurality of extraction layers are arranged at intervals along the stacking direction. The connection portions extend in the stacking direction, and one connection portion is connected to one lead-out layer. The plurality of connecting parts are positioned on one side of the plurality of storage structures in the second direction, and the plurality of connecting parts are arranged at intervals along the first direction. In some embodiments, the first transistor structure includes a channel layer and a gate dielectric layer, the gate dielectric layer being located between the channel layer and the gate. The gate of the first transistor structure includes a first gate electrode located on one side of the channel layer in the stacking direction and a second gate electrode located on the other side of the channel layer in the stacking direction. The extraction layer comprises a first conductive layer and a second conductive layer, wherein the first conductive layer is connected with a first grid electrode of the first transistor structure, and the second conductive layer is connected with a second grid electrode of the first transistor structure. In some embodiments, the connection includes a first connection and a second connection. The first connecting portion is located between the first conductive layer and the second conductive layer, and the first connecting portion is connected with both the first conductive layer and the second conductive layer. The second connecting portion is located at one side of the first connecting portion in the stacking direction, extends in the stacking direction, and is connected with the first connecting portion. In some embodiments, the connection includes a third connection and a fourth connection. The third connection portion extends in the stacking direction and is connected to the first conductive layer. The fourth connection portion extends in the stacking direction and is connected to the second conductive layer. In some embodiments, the first conductive layer is co-layer with a first gate of the first transistor structure and the second conductive layer is co-layer with a second gate of the first transistor structure. In some embodiments, the third connection portion is located at a side of the first conductive layer facing away from the second conductive layer, and a boundary of the third connection portion near an end of the first conductive layer is located inside a boundary of the third connection portion facing away from the end of the first conductive layer. The fourth connecting portion is located one side of the second conductive layer, which faces away from the first conductive layer, and the boundary of one end, close to the second conductive layer, of the fourth connecting portion is located inside the boundary of one end, which faces away from the second conductive layer, of the fourth connecting portion. In some embodiments, at least a portion of the third connection portion and the fourth connection portion are disposed opposite in the stacking direction. In some embodiments,