CN-122002781-A - Semiconductor structure, preparation method thereof and storage system

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips. The semiconductor structure includes a first transistor structure, a capacitive unit, and a second transistor structure. The capacitor unit includes a first internal electrode, a second internal electrode, a first external electrode, a second external electrode, a common electrode, and a dielectric layer. The first internal electrode and the second internal electrode are arranged at intervals along a first direction perpendicular to the stacking direction, the first internal electrode is connected with the first transistor structure, and the second internal electrode is connected with the second transistor structure. The first outer electrode surrounds the first inner electrode and the second outer electrode surrounds the second inner electrode. The common electrode is positioned between the first inner electrode and the second inner electrode and is connected with the first outer electrode and the second outer electrode. The dielectric layer is positioned between the first inner electrode and the first outer electrode, and between the second inner electrode and the second outer electrode. The semiconductor structure is applied to the dynamic random access memory to realize the reading and writing of data.

Inventors

• XIA ZHILIANG
• DU XIAOLONG
• ZHOU WENXI
• HUO ZONGLIANG

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260508

Application Date

20241031

Claims (20)

1. 1. A semiconductor structure, comprising: A memory structure including a first transistor structure, a capacitance unit, and a second transistor structure stacked in a first direction perpendicular to a stacking direction, the capacitance unit being located between the first transistor structure and the second transistor structure; The capacitor unit comprises a first inner electrode, a second inner electrode, a first outer electrode, a second outer electrode, a common electrode and a dielectric layer, wherein the first inner electrode and the second inner electrode are arranged at intervals along the first direction, the first inner electrode is close to the first transistor structure compared with the second inner electrode, the first inner electrode is connected with the first transistor structure, the second inner electrode is connected with the second transistor structure, the first outer electrode surrounds the first inner electrode, the second outer electrode surrounds the second inner electrode, the common electrode is located between the first inner electrode and the second inner electrode and connected with the first outer electrode and the second outer electrode, and the dielectric layer is located between the first inner electrode and the first outer electrode and between the second inner electrode and the second outer electrode.
2. 2. The semiconductor structure of claim 1, wherein, The first transistor structure comprises a channel layer, a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned between the channel layer and the gate electrode, and the material of the channel layer comprises indium gallium zinc oxide.
3. 3. The semiconductor structure of claim 2, wherein, The channel layer extends in the first direction, and the dimension of the channel layer in the second direction increases and decreases in the first direction, wherein the second direction passes through a plane in which the stacking direction and the first direction lie.
4. 4. The semiconductor structure of claim 2, wherein, The channel layer extends in the first direction, and a dimension of the channel layer in the stacking direction is greater than or equal to 2nm and less than or equal to 10nm.
5. 5. The semiconductor structure of claim 3 or 4, wherein, The gate includes a first gate electrode located at one side of the channel layer in the stacking direction and a second gate electrode located at the other side of the channel layer in the stacking direction.
6. 6. The semiconductor structure of claim 5, wherein, The memory structure further includes a first insulating portion between the first external electrode and the gate electrode of the first transistor structure, and a second insulating portion between the second external electrode and the gate electrode of the second transistor structure.
7. 7. The semiconductor structure of claim 6, wherein the semiconductor structure further comprises: The extraction layers are positioned on at least one side of the capacitor unit in the second direction, and are connected with the grid electrode of each first transistor structure and the grid electrode of each second transistor structure, wherein the second direction passes through the plane where the stacking direction and the first direction are positioned.
8. 8. The semiconductor structure of claim 7, wherein, The extraction layer comprises a first conductive layer and a second conductive layer, the first conductive layer is connected with the first grid electrode of each first transistor structure and the first grid electrode of each second transistor structure, and the second conductive layer is connected with the second grid electrode of each first transistor structure and the second grid electrode of each second transistor structure.
9. 9. The semiconductor structure of claim 7, wherein, The number of the storage structures is multiple, the storage structures are arranged into layers along the second direction and are arranged into multiple layers along the stacking direction, and the common electrodes of the storage structures are connected into an integrated structure; the number of the extraction layers is multiple, the extraction layers are arranged at intervals along the stacking direction, one extraction layer is positioned on at least one side of a capacitor unit of one storage structure in the second direction, and the extraction layer is connected with the grid electrode of each first transistor structure and the grid electrode of each second transistor structure in the same layer.
10. 10. The semiconductor structure of claim 9, wherein the semiconductor structure comprises a silicon nitride layer, The semiconductor structure further comprises a plurality of first bit lines and a plurality of second bit lines, wherein the first bit lines are positioned on one side of the first transistor structure, which is away from the first inner electrode, extend along the stacking direction and are connected with a row of channel layers of the first transistor structure, and the plurality of first bit lines are arranged at intervals along the second direction; The second bit line is located at one side of the second transistor structure, which is away from the second internal electrode, extends along the stacking direction, is connected with a row of channel layers of the second transistor structure, and is arranged at intervals along the second direction.
11. 11. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises: a first connection portion extending in the stacking direction, the first connection portion being connected to the extraction layer; A second connection portion extending in the stacking direction and connected to the first bit line or the second bit line; And a third connection portion extending in the stacking direction and connected to the common electrode.
12. 12. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises: A third insulating part located at one side of the common electrode in the first direction and located between the first internal electrodes of two adjacent columns of the memory structure; a fourth insulating portion located at a side of the third insulating portion facing away from the common electrode, and located at least one side of the first bit line in the second direction; A fifth insulating part located at the other side of the common electrode in the first direction and between the second internal electrodes of two adjacent columns of the memory structures; A sixth insulating portion located at a side of the fifth insulating portion facing away from the common electrode, and located at least one side of the second bit line in the second direction; and a seventh insulating part, wherein the seventh insulating part is positioned at two sides of the capacitor units of the storage structures in the second direction.
13. 13. The semiconductor structure of any one of claims 7-12, wherein the semiconductor structure further comprises: the storage structure, the extraction layer, the third insulation part, the fourth insulation part, the fifth insulation part, the sixth insulation part and the seventh insulation part are all embedded in the insulation layer.
14. 14. The semiconductor structure of claim 13, wherein, The third insulating part and the fourth insulating part extend along the stacking direction, and each comprise a first sub insulating part and a second sub insulating part which are alternately stacked along the stacking direction, wherein the size of the first sub insulating part in the direction perpendicular to the stacking direction is larger than the size of the second sub insulating part in the direction perpendicular to the stacking direction; The first transistor structure comprises a first insulating part, a second insulating part, a third insulating part, a fourth insulating part, a channel layer, a first insulating layer, a second insulating layer, a first transistor structure, a second transistor structure, a third transistor structure, a fourth transistor structure, a first transistor structure, a second transistor structure and a third transistor structure.
15. 15. A method of fabricating a semiconductor structure, comprising: Forming a capacitor unit, wherein the capacitor unit comprises a first inner electrode, a second inner electrode, a first outer electrode, a second outer electrode, a common electrode and a dielectric layer, the first inner electrode and the second inner electrode are arranged at intervals along the first direction, the first outer electrode surrounds the first inner electrode, the second outer electrode surrounds the second inner electrode, the common electrode is positioned between the first inner electrode and the second inner electrode and is connected with the first outer electrode and the second outer electrode, and the dielectric layer is positioned between the first inner electrode and the first outer electrode and between the second inner electrode and the second outer electrode; And forming a first transistor structure and a second transistor structure to form a storage structure, wherein the first transistor structure and the second transistor structure are positioned on two sides of the capacitor unit in a first direction perpendicular to the stacking direction, the first inner electrode is closer to the first transistor structure than the second inner electrode, the first inner electrode is connected with the first transistor structure, and the second inner electrode is connected with the second transistor structure.
16. 16. The method of manufacturing a semiconductor structure of claim 15, further comprising: Forming a stacked structure including sub-insulating layers and sacrificial layers alternately stacked in the stacking direction, the sacrificial layers including two first sacrificial layers and a second sacrificial layer disposed in a stacked manner, the second sacrificial layer being located between the two first sacrificial layers; Forming two seventh insulating parts and at least one insulating structure, wherein the insulating structure is arranged between the two seventh insulating parts at intervals, and the seventh insulating parts and the insulating structure extend along the first direction and penetrate through the stacking structure along the stacking direction; Forming a first bar-shaped groove penetrating through the insulating structure along a second direction and penetrating through the stacking structure along the stacking direction so as to separate the insulating structure into a third insulating part and a fifth insulating part, wherein the sacrificial layer is exposed out of the first bar-shaped groove; And forming a fourth insulating part and a sixth insulating part, wherein the fourth insulating part is arranged at one side of the third insulating part, which is away from the fifth insulating part, and the sixth insulating part is arranged at one side of the fifth insulating part, which is away from the third insulating part.
17. 17. The method of fabricating a semiconductor structure of claim 16, wherein forming a capacitor cell comprises: Removing the second sacrificial layer between the two seventh insulating parts through the first strip-shaped grooves to form a first gap layer; forming a first internal electrode and a second internal electrode within the first gap layer, wherein the first internal electrode is closer to the third insulating portion than the second internal electrode; Removing the first sacrificial layer between the two seventh insulating parts through the first strip-shaped grooves to form a second gap layer; And forming a dielectric layer and a conductive filling part in the second gap layer and the first strip-shaped groove in sequence, wherein the conductive filling part surrounds the first inner electrode and the second inner electrode, the dielectric layer is positioned between the conductive filling part and the first inner electrode and between the conductive filling part and the second inner electrode, a part of the conductive filling part surrounding the first inner electrode serves as a first outer electrode, a part of the conductive filling part surrounding the second inner electrode serves as a second outer electrode, and a part of the conductive filling part positioned in the first strip-shaped groove serves as a common electrode.
18. 18. The method of fabricating a semiconductor structure of claim 17, wherein forming the first transistor structure and the second transistor structure comprises: Removing part of the first sacrificial layer to form a third gap layer, wherein the third gap layer is arranged around the capacitor unit, and the reserved first sacrificial layer is used as a first insulating part and a second insulating part, wherein the first insulating part is positioned at one side of the first internal electrode, which is away from the common electrode, and the second insulating part is positioned at one side of the second internal electrode, which is away from the common electrode; A dielectric structure and a conductive structure are sequentially formed in the third gap layer, wherein the dielectric structure surrounds the conductive structure, the part of the conductive structure, which is positioned at the two sides of the capacitor unit in the first direction, is a grid electrode, the part of the conductive structure, which is positioned at the two sides of the capacitor unit in the second direction, is a leading-out layer, and the part of the dielectric structure surrounding the grid electrode is a grid dielectric layer; Removing the second sacrificial layer at one side of the first internal electrode, which is away from the common electrode, so as to form a fourth gap layer; Removing the second sacrificial layer on one side of the second internal electrode, which is away from the common electrode, so as to form a fifth gap layer; And forming a channel layer in the fourth gap layer and the fifth gap to form the first transistor structure and the second transistor structure.
19. 19. The method of manufacturing a semiconductor structure of claim 18, further comprising: forming a first bit line, wherein the first bit line is positioned at one side of a channel layer of the first transistor structure, which is away from the first capacitor unit; and forming a second bit line, wherein the second bit line is positioned on one side of the channel layer of the second transistor structure, which is away from the second capacitor unit.
20. 20. A storage system, comprising: The semiconductor structure of any one of claims 1-14; And a controller coupled to the semiconductor structure to control the semiconductor structure to store data.

Description

Semiconductor structure, preparation method thereof and storage system Technical Field The disclosure relates to the technical field of semiconductor chips, and in particular relates to a semiconductor structure, a preparation method thereof and a storage system. Background Dynamic random access memory (dynamic random access memory, DRAM) is scaled to smaller sizes as process technology, circuit design, and manufacturing processes improve. However, as the feature size of memory cells within a memory approaches a lower limit, planar processing and fabrication techniques become challenging and costly, resulting in densities of memory cells approaching an upper limit. Therefore, how to further realize the miniaturization of the DRAM becomes a technical problem that is difficult for the current technicians to solve. Disclosure of Invention Embodiments of the present disclosure provide a semiconductor structure, a method of manufacturing the same, and a memory system. The embodiment of the disclosure adopts the following technical scheme: In one aspect, embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a memory structure. The memory structure includes a first transistor structure, a capacitance unit, and a second transistor structure stacked in a first direction perpendicular to the stacking direction, the capacitance unit being located between the first transistor structure and the second transistor structure. The capacitor unit includes a first internal electrode, a second internal electrode, a first external electrode, a second external electrode, a common electrode, and a dielectric layer. The first inner electrode and the second inner electrode are arranged at intervals along the first direction, the first inner electrode is close to the first transistor structure compared with the second inner electrode, the first inner electrode is connected with the first transistor structure, and the second inner electrode is connected with the second transistor structure. The first outer electrode surrounds the first inner electrode and the second outer electrode surrounds the second inner electrode. The common electrode is positioned between the first inner electrode and the second inner electrode and is connected with the first outer electrode and the second outer electrode. The dielectric layer is positioned between the first inner electrode and the first outer electrode, and between the second inner electrode and the second outer electrode. In some embodiments, the first transistor structure includes a channel layer, a gate dielectric layer, and a gate electrode, the gate dielectric layer being located between the channel layer and the gate electrode, wherein a material of the channel layer includes indium gallium zinc oxide. In some embodiments, the channel layer extends in a first direction, and the channel layer increases in size in a second direction before decreasing in size in the first direction. Wherein the second direction passes through a plane in which the lamination direction and the first direction lie. In some embodiments, the channel layer extends along the first direction, and a dimension of the channel layer in the stacking direction is greater than or equal to 2nm and less than or equal to 10nm. In some embodiments, the gate includes a first gate electrode located at one side of the channel layer in the stacking direction and a second gate electrode located at the other side of the channel layer in the stacking direction. In some embodiments, the memory structure further includes a first insulating portion and a second insulating portion. The first insulating part is positioned between the first external electrode and the gate electrode of the first transistor structure, and the second insulating part is positioned between the second external electrode and the gate electrode of the second transistor structure. In some embodiments, the semiconductor structure further includes an extraction layer. The extraction layer is positioned on at least one side of the capacitor unit in the second direction, and the extraction layer is connected with the grid electrode of each first transistor structure and the grid electrode of each second transistor structure. Wherein the second direction passes through a plane in which the lamination direction and the first direction lie. In some embodiments, the extraction layer includes a first conductive layer and a second conductive layer. The first conductive layer is connected with the first grid electrode of each first transistor structure and the first grid electrode of each second transistor structure, and the second conductive layer is connected with the second grid electrode of each first transistor structure and the second grid electrode of each second transistor structure. In some embodiments, the number of memory structures is a plurality, the plurality of memory structures are arranged in layers alo