CN-122002782-A - Semiconductor device, manufacturing method thereof, memory unit, reading and writing method and memory

Abstract

The embodiment of the disclosure provides a semiconductor device, a preparation method thereof, a storage unit, a read-write method and a memory. The semiconductor device comprises a substrate, a storage unit and a control unit, wherein the substrate comprises a substrate and a stacking structure arranged on the substrate, the stacking structure comprises a first insulating layer and a second insulating layer which are alternately arranged, a plurality of first hole structures and second hole structures which penetrate through the stacking structure and are arranged along a first direction, the first direction is parallel to the substrate, the storage unit comprises a first substructure arranged in the first hole structures and a second substructure arranged in the second hole structures, the first substructure comprises a reading transistor and a capacitor, the first substructure is arranged in the first insulating layer or the second insulating layer, the second substructure comprises a first transistor and a second transistor, and the second substructure is arranged in the first insulating layer or the second insulating layer.

Inventors

• ZHU ZHENGYONG
• KANG BOWEN
• ZHAO CHAO

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260508

Application Date

20241101

Claims (20)

1. 1. A semiconductor device, comprising: A base including a substrate and a stacked structure disposed on the substrate, the stacked structure including first insulating layers and second insulating layers alternately disposed; A plurality of first and second aperture structures extending through the stacked structure and disposed along a first direction, the first direction being parallel to the substrate; A memory cell including a first substructure disposed in the first aperture structure and a second substructure disposed in the second aperture structure; the first substructure includes a read transistor and a capacitor, the first substructure being located in the first insulating layer or the second insulating layer; The second substructure includes a first transistor and a second transistor, the second substructure being located in the first insulating layer or the second insulating layer.
2. 2. The semiconductor device of claim 1, wherein the first hole structure includes a read word line extending through the stacked structure, the first substructure including a capacitor surrounding the read word line and a read transistor partially surrounding the capacitor.
3. 3. The semiconductor device of claim 2, wherein the first substructure comprises a first dielectric layer and a first conductive layer surrounding the read word line, and a first gate dielectric layer and a first semiconductor layer partially surrounding the first conductive layer.
4. 4. The semiconductor device of claim 3, wherein the second hole structure includes a write word line extending through the stacked structure, the first transistor and the second transistor are a unitary structure, and the unitary structure surrounds the write word line.
5. 5. The semiconductor device of claim 4, wherein the unitary structure comprises a second gate dielectric layer and a second semiconductor layer surrounding the write word line.
6. 6. The semiconductor device according to claim 5, wherein the second semiconductor layer is in contact with the first conductive layer.
7. 7. The semiconductor device according to claim 5, further comprising a bit line structure extending in the first direction, wherein a plurality of the memory cells arranged in the first direction are connected to the same bit line structure; The bit line structure comprises a first bit line arranged on a first side of the memory cell and a second bit line arranged on a second side of the memory cell, wherein the first side and the second side are two opposite sides of the memory cell in a second direction, the second direction intersects the first direction, and the second direction is parallel to the substrate.
8. 8. The semiconductor device according to claim 7, wherein the first bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell, and wherein the second bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell.
9. 9. The semiconductor device of claim 1, wherein a second dielectric layer is included between two adjacent memory cells along the first direction.
10. 10. The semiconductor device according to claim 5, wherein a material of the second semiconductor layer comprises a metal oxide semiconductor, wherein the metal oxide semiconductor comprises at least one element of indium, gallium, zinc, tin, and tungsten.
11. 11. The semiconductor device according to claim 3, wherein a material of the first semiconductor layer comprises a single crystal semiconductor, a polycrystalline semiconductor, or a metal oxide semiconductor.
12. 12. The semiconductor device according to claim 3, wherein an outer peripheral shape of the first semiconductor layer is the same as an inner peripheral shape of the first semiconductor layer.
13. 13. The semiconductor device of claim 2, wherein a size of the read word line at the first insulating layer is greater than a size of the read word line at the second insulating layer when the first substructure is located at the first insulating layer; when the first substructure is located on the second insulating layer, the size of the read word line on the second insulating layer is larger than the size of the read word line on the first insulating layer.
14. 14. A method of manufacturing a semiconductor device, comprising: Providing a substrate, wherein the substrate comprises a substrate and a stacked structure formed on the substrate, and the stacked structure comprises a first insulating layer and a second insulating layer which are alternately arranged; Forming a plurality of first hole structures and second hole structures penetrating the stacked structure and arranged along a first direction, wherein the first direction is parallel to the substrate; The first hole structure includes first sub-structures disposed in the first insulating layer or the second insulating layer, each of the first sub-structures including a read transistor and a capacitor; The second hole structure comprises second substructures arranged in the first insulating layer or the second insulating layer, each second substructure comprises a first transistor and a second transistor, and the first substructures and the second substructures form a memory unit.
15. 15. The method of preparing according to claim 14, wherein forming the first pore structure comprises: Forming a first hole penetrating through the stacked structure, wherein when the first substructure is positioned on the first insulating layer, the size of the first hole is larger than that of the first hole on the second insulating layer, and when the first substructure is positioned on the second insulating layer, the size of the first hole on the second insulating layer is larger than that of the first hole on the first insulating layer; the first hole structure is formed through the first hole, the first hole structure further includes a read word line penetrating through the stacked structure, and the capacitor surrounds the read word line.
16. 16. The method of manufacturing according to claim 15, wherein the forming a first hole through the stacked structure comprises: Forming a first initial hole penetrating through the stacked structure, and laterally etching the first insulating layer or the second insulating layer through the first initial hole to form a first lateral groove surrounding the first initial hole, wherein the first initial hole and the first lateral groove form the first hole.
17. 17. The method of preparing according to claim 16, wherein said forming said first pore structure through said first pore comprises: Sequentially forming a read transistor and the capacitor which cover the bottom of the first transverse groove; Conductive material is deposited through the first initial hole to form the read word line filling the first initial hole.
18. 18. The method of preparing according to claim 16, wherein said forming said first pore structure through said first pore comprises: sequentially forming the read transistor and the capacitor which cover the bottom and the side wall of the first transverse groove; Depositing a conductive material through the first initial hole to form the read word line filling the first lateral recess and the first initial hole; The first substructure is located on the first insulating layer, the read word line is larger in size on the first insulating layer than the read word line is located on the second insulating layer, and the read word line is larger in size on the second insulating layer than the read word line is located on the first insulating layer.
19. 19. The method of preparing according to claim 14, wherein forming the second pore structure comprises: Forming a second hole penetrating through the stacked structure, wherein the second hole is larger than the second hole in the first insulating layer when the second substructure is positioned on the first insulating layer, and the second hole is larger than the second hole in the first insulating layer when the second substructure is positioned on the second insulating layer; The second hole structure is formed through the second hole, the second hole structure further comprises a writing line penetrating through the stacked structure, the first transistor and the second transistor are of an integrated structure, and the integrated structure surrounds the writing line.
20. 20. The method of manufacturing according to claim 19, wherein the forming of the second hole through the stacked structure comprises: Forming a second initial hole penetrating through the stacked structure, wherein the projection of the second initial hole on the substrate is not overlapped with the projection of the first hole structure on the substrate; And carrying out lateral etching on the first insulating layer or the second insulating layer and the read transistor through the second initial hole until part of the capacitor is exposed so as to form a second lateral groove surrounding the second initial hole, wherein the second initial hole and the second lateral groove form the second hole.

Description

Semiconductor device, manufacturing method thereof, memory unit, reading and writing method and memory Technical Field The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor device, a manufacturing method thereof, a storage unit, a read-write method and a memory. Background With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices included in a single chip are increasing, so that small differences in process production may affect the performance of the devices. In order to reduce the cost of the product as much as possible, it is desirable to make as many device cells as possible on a limited substrate. Since moore's law emerged, various semiconductor structural designs and process optimizations have been proposed in the industry to meet the needs of people for current products. Disclosure of Invention In view of this, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, a memory cell, a method for reading and writing, and a memory. In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows: In a first aspect, an embodiment of the disclosure provides a semiconductor device, including a substrate and a stacked structure disposed on the substrate, the stacked structure including a first insulating layer and a second insulating layer alternately disposed, a plurality of first hole structures and second hole structures penetrating the stacked structure and disposed along a first direction, the first direction being parallel to the substrate, a memory cell including a first substructure disposed in the first hole structures and a second substructure disposed in the second hole structures, the first substructure including a read transistor and a capacitor, the first substructure being disposed in the first insulating layer or the second insulating layer, the second substructure including a first transistor and a second transistor, the second substructure being disposed in the first insulating layer or the second insulating layer. In some embodiments, the first hole structure includes a read word line extending through the stacked structure, and the first substructure includes a capacitor surrounding the read word line and a read transistor partially surrounding the capacitor. In some embodiments, the first substructure includes a first dielectric layer and a first conductive layer surrounding the read word line, and a first gate dielectric layer and a first semiconductor layer partially surrounding the first conductive layer. In some embodiments, the second hole structure includes a write word line extending through the stacked structure, the first transistor and the second transistor are a unitary structure, and the unitary structure surrounds the write word line. In some embodiments, the unitary structure includes a second gate dielectric layer and a second semiconductor layer surrounding the write word line. In some embodiments, the second semiconductor layer is in contact with the first conductive layer. In some embodiments, the memory device further includes a bit line structure extending along a first direction, a plurality of memory cells arranged along the first direction being connected to the same bit line structure, the bit line structure including a first bit line disposed on a first side of the memory cells and a second bit line disposed on a second side of the memory cells, the first side and the second side being opposite sides of the memory cells in a second direction, the second direction intersecting the first direction, the second direction being parallel to the substrate. In some embodiments, the first bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell, and the second bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell. In some embodiments, a second dielectric layer is included between two adjacent memory cells along the first direction. In some embodiments, the material of the second semiconductor layer comprises a metal oxide semiconductor, wherein the metal oxide semiconductor comprises at least one element of indium, gallium, zinc, tin, and tungsten. In some embodiments, the material of the first semiconductor layer comprises a single crystal semiconductor, a polycrystalline semiconductor, or a metal oxide semiconductor. In some embodiments, the outer perimeter shape of the first semiconductor layer is the same as the inner perimeter shape of the first semiconductor layer. In some embodiments, the read word line has a larger dimension in the first insulating layer than the read word line has in the second insulating layer when the first substructure is located in the first insulating layer, and the read word line has a larger dimension in