CN-122002785-A - Embedded memory and electronic equipment

Abstract

The embodiment of the application discloses an embedded memory and electronic equipment, and relates to the technical field of semiconductors. The embedded memory has a logical area and a memory area. The embedded memory includes a substrate, a storage capacitor, and a transistor. The substrate has a first surface. The transistor is located on the first surface. The transistor comprises a channel part and a grid electrode, wherein the grid electrode is positioned between one side surface of the channel part far from the substrate and one side surface close to the substrate and positioned on at least one side of the channel part. The transistor comprises a first transistor and a second transistor, wherein the first transistor is positioned in a logic area and used for forming a logic operation circuit, and the second transistor and the storage capacitor are positioned in a storage area and connected with each other and used for forming a memory. The channel length of the channel portion of the second transistor is greater than the channel length of the channel portion of the first transistor. The differential design of the channel lengths of the first transistor and the second transistor can simultaneously meet the performance requirements of the logic operation circuit and the memory.

Inventors

• HU XIANG
• Xiao Zhuocong
• YU WEI
• CHEN JUNSHU
• ZHANG ZHUOCHENG
• DONG YAOQI
• XU JUNHAO

Assignees

• 华为技术有限公司

Dates

Publication Date

20260508

Application Date

20241101

Claims (20)

1. 1. An embedded memory, wherein the embedded memory has a logic area and a memory area, the logic area being located on at least one side of the memory area; The embedded memory includes: A substrate having a first surface; A storage capacitor which is positioned in the storage area and embedded in the substrate; A plurality of transistors on the first surface, the transistors including a channel portion and a gate electrode, the gate electrode being located between a side surface of the channel portion remote from the substrate and a side surface close to the substrate and being located on at least one side of the channel portion in a first direction, the first direction being perpendicular to the first surface, the plurality of transistors including a first transistor and a second transistor, the first transistor being located in the logic region and the second transistor being located in the storage region; wherein a channel length of a channel portion of the second transistor is greater than a channel length of a channel portion of the first transistor.
2. 2. The embedded memory of claim 1, wherein the channel portion of the second transistor comprises: a first sub-portion extending along the first direction; The second sub-portion is positioned between the substrate and the first sub-portion and extends along a direction parallel to the first surface, the second sub-portion is provided with a first end and a second end which are opposite, the first end of the second sub-portion is connected with the first sub-portion, and the second end of the second sub-portion exceeds the first sub-portion along the extending direction of the second sub-portion.
3. 3. The embedded memory of claim 2, wherein a dimension of the first sub-portion in the first direction is equal to a dimension of a channel portion of the first transistor in the first direction.
4. 4. The embedded memory of claim 2 or 3, wherein the transistor further comprises a first pole and a second pole, the first pole being connected to a side surface of the channel portion remote from the substrate; A second pole of the first transistor is positioned between the substrate and the channel part of the first transistor and is connected with one side surface of the channel part of the first transistor, which is close to the substrate; the second pole of the second transistor is positioned at one side of the second end of the second sub-part far away from the first end of the second sub-part and is connected with the second end of the second sub-part.
5. 5. The embedded memory of claim 4, wherein the first sub-portion further extends in a second direction, a second end of the second sub-portion being located on a side of the first sub-portion in a third direction, the second direction and the third direction intersecting and each being parallel to the first surface.
6. 6. The embedded memory of claim 5, wherein the second transistor further comprises a dummy sub-portion extending in the first direction and extending in the second direction; The dummy sub-portion is located between the first sub-portion and a second pole of the second transistor, and is connected to a side of the second sub-portion away from the substrate.
7. 7. The embedded memory of claim 6, wherein the dummy sub-portion and the first sub-portion and the second sub-portion are in a unitary structure.
8. 8. The embedded memory according to claim 6 or 7, wherein the second transistor further comprises a dummy electrode connected to a side surface of the dummy sub-portion remote from the substrate; The dummy electrode and the second electrode are arranged on the same layer.
9. 9. The embedded memory according to any one of claims 5-8, wherein the second transistor and the storage capacitor connected to the second transistor constitute a memory cell; Orthographic projections of two adjacent storage units on the first surface along the third direction are symmetrically arranged about a first symmetry axis extending along the second direction.
10. 10. The embedded memory of claim 4, wherein the first sub-portion further extends in a second direction, a second end of the second sub-portion being located on a side of the first sub-portion in the second direction, the second direction being parallel to the first surface.
11. 11. The embedded memory of claim 1, wherein the transistor further comprises a first pole and a second pole, the first pole and the second pole being connected to opposite ends of the channel portion, respectively, along the first direction; The first pole and the second pole of the first transistor are partially opposite and the first pole and the second pole of the second transistor are staggered along the first direction.
12. 12. The embedded memory of claim 11, wherein the channel portion further extends in a second direction, the second direction being parallel to the first surface; The second pole of the first transistor is positioned between the substrate and the channel part of the first transistor and is connected with one side surface of the channel part of the first transistor, which is close to the substrate; The first pole and the second pole of the second transistor are arranged along the second direction, the first pole of the second transistor is connected to a part of the surface of one side of the channel part of the second transistor, which is far away from the substrate, and the second pole of the second transistor is connected with the side surface of the channel part of the second transistor.
13. 13. The embedded memory according to claim 11 or 12, wherein a dimension of the channel portion of the first transistor in the first direction is equal to a dimension of the channel portion of the second transistor in the first direction.
14. 14. The embedded memory according to any one of claims 10-13, wherein the second transistor and the storage capacitor connected to the second transistor constitute a memory cell; the orthographic projections of two adjacent storage units on the first surface along the second direction are symmetrically arranged about a second symmetrical axis extending along a third direction, and the third direction and the second direction intersect and are parallel to the first surface.
15. 15. The embedded memory of claim 14, wherein two of the memory cells adjacent in the second direction are a first memory cell and a second memory cell, respectively; A channel part of a second transistor in the first memory cell and the second memory cell is positioned between the second poles of the second transistors in the first memory cell and the second memory cell; And the grid electrodes of the second transistors in the first storage unit and the second storage unit are connected and are in an integrated structure.
16. 16. The embedded memory of claim 1, wherein the transistor further comprises a first pole and a second pole, the first pole being connected to a side surface of the channel portion remote from the substrate, the second pole being located between the substrate and the channel portion and being connected to a side surface of the channel portion proximate to the substrate; the channel portion of the first transistor has a smaller dimension in the first direction than the channel portion of the second transistor.
17. 17. The embedded memory of any one of claims 4-16, wherein a second pole of the second transistor is connected to the storage capacitor; In the first direction, a second pole of the second transistor is opposite to the storage capacitor portion.
18. 18. The embedded memory of any of claims 4-16, wherein a second pole of the second transistor is offset from the storage capacitor along the first direction; the embedded memory further comprises a connecting part positioned in the storage area, and the connecting part is connected with the second pole of the second transistor and the storage capacitor.
19. 19. The embedded memory of claim 18, further comprising a first contact connected to a side surface of the gate remote from the substrate and a second contact connected to a side surface of the first pole remote from the substrate; the connecting part, the first contact and the second contact are arranged on the same layer.
20. 20. The embedded memory of any of claims 4-19, wherein the first pole, the second pole, and the channel portion in the same transistor are of unitary construction with the substrate.

Description

Embedded memory and electronic equipment Technical Field The present application relates to the field of semiconductor technologies, and in particular, to an embedded memory and an electronic device. Background An embedded memory (embedded memory) is a free-standing memory (standalone memory) integrated on the same chip as the logic circuits. Compared with a stand-alone memory, the embedded memory has the advantages of higher access speed, higher bandwidth, lower delay and the like. However, in embedded memories, the characteristics requirements of transistors applied to free-standing memories are different from those of transistors applied to logic circuits. With the evolution of advanced technology nodes, the feature size of transistors is continuously reduced, and the designs of transistors applied to independent memories and transistors applied to logic circuits are contradictory, so that the performance requirements of the independent memories and the logic circuits are difficult to meet at the same time. Therefore, how to balance the performances of the free-standing memory and the logic operation circuit in the embedded memory is called a technical problem to be solved. Disclosure of Invention The embodiment of the application provides an embedded memory and electronic equipment, which are used for carrying out differential design on transistors positioned in a logic area and a storage area so as to simultaneously meet the performance requirements of the parts of the embedded memory positioned in the logic area and the storage area. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: In a first aspect, an embedded memory, such as an embedded dynamic random access memory, is provided. The embedded memory is provided with a logic area and a storage area, wherein the logic area is positioned on at least one side of the storage area. The embedded memory includes a substrate, a storage capacitor, and a plurality of transistors. The substrate has a first surface. The storage capacitor is located in the storage region and embedded in the substrate. The plurality of transistors is located on the first surface. The transistor comprises a channel part and a gate electrode, wherein the gate electrode is positioned between one side surface of the channel part far from the substrate and one side surface close to the substrate along a first direction and positioned on at least one side of the channel part. The first direction is perpendicular to the first surface. The plurality of transistors includes a first transistor and a second transistor, a channel length of a channel portion of the second transistor being greater than a channel length of a channel portion of the first transistor. The first transistor is located in the logic region, and the second transistor is located in the storage region. The first transistor is used for forming a logic operation circuit, the second transistor is connected with a storage capacitor to form a storage unit, and the plurality of storage units are used for forming a memory. According to the embedded memory provided by some embodiments of the application, the channel length of the channel part of the first transistor positioned in the logic area and the channel length of the channel part of the second transistor positioned in the storage area are arranged in a differentiated mode, namely, the channel length of the channel part of the first transistor is smaller than that of the channel part of the second transistor, so that the first transistor has a faster on/off speed, the second transistor has a smaller leakage current, the requirements of a logic operation circuit on a higher data processing speed can be met, the requirements of a dynamic refreshing mechanism of the memory can be met, and the performance requirements of the logic operation circuit and the memory are balanced. In addition, the storage capacitor is embedded in the substrate, so that at least one part of the storage capacitor is positioned below the second transistor, on one hand, the preparation process of the transistor and the preparation process of the storage capacitor can be separated, the preparation of a channel part of the transistor is prevented from being influenced, the differential preparation of the channel length of the channel part of the first transistor and the channel length of the channel part of the second transistor is prevented from being influenced, on the other hand, the influence on the thermal budget and the rear-stage connecting line of the logic operation circuit can be reduced, on the other hand, the preparation difficulty of the embedded memory is reduced in terms of technology, on the other hand, the capacitance of the storage capacitor is increased, and the read-write window is increased. In a possible design manner of the first aspect, the channel portion of the second transistor includes a first sub-portion a