CN-122002786-A - Semiconductor structure and preparation method thereof

CN122002786ACN 122002786 ACN122002786 ACN 122002786ACN-122002786-A

Abstract

A semiconductor structure comprises a plurality of stacked substructures arranged on a substrate at intervals along a first direction, wherein each stacked substructure comprises an active layer and a first dielectric layer which are alternately stacked along the vertical direction, a word line layer, a first word line isolation structure and a second word line isolation structure, the word line substructures are arranged on the substrate, the bottom ends of the word line layer are lower than the bottom surfaces of the stacked substructures, the first word line isolation structure is arranged between the stacked substructures, the second word line isolation structure comprises a first isolation part, a second isolation part and a third isolation part which are sequentially connected, the first isolation part and the third isolation part extend along the vertical direction, the second isolation part extends along the second direction and is connected with the bottoms of the first isolation part and the third isolation part, and the bottom ends of the word line layer are connected with the top of the second isolation part. The semiconductor structure can improve the reliability of the semiconductor structure.

Inventors

WANG HONG
WAN GUOLIANG
LI XIAOJIE

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20241104

Claims (10)

1. A semiconductor structure, comprising: the substrate comprises a substrate, a plurality of stacking substructures, a plurality of first dielectric layers and a plurality of second dielectric layers, wherein the stacking substructures are positioned on the substrate and are arranged at intervals along a first direction, and each stacking substructure comprises an active layer and a first dielectric layer which are alternately stacked along a vertical direction; The word line layer is positioned on the top surface of the stacked substructure and the side wall perpendicular to the first direction, and the bottom end of the word line layer is lower than the bottom surface of the stacked substructure; A first word line isolation structure located between the stacked sub-structures; The second word line isolation structure comprises a first isolation part, a second isolation part and a third isolation part which are sequentially connected, wherein the first isolation part and the third isolation part extend along the vertical direction, the second isolation part extends along the second direction and is connected with the bottoms of the first isolation part and the third isolation part, and the bottom of the word line layer is connected with the top of the second isolation part.
2. The semiconductor structure of claim 1, wherein the substrate includes raised portions under the stacked substructure, the second isolation portions are between the raised portions, and a top surface of the second isolation portions is lower than a top surface of the raised portions.
3. The semiconductor structure of claim 2, further comprising: The gate dielectric layer covers the side wall of the active layer perpendicular to the first direction; The substrate protection layer covers the side wall and the bottom of the groove formed between the adjacent convex parts, and is clamped between the second isolation part and the substrate; The thickness of the substrate protection layer is larger than that of the gate dielectric layer, and the ratio of the thickness of the substrate protection layer to that of the first dielectric layer is in the range of 0.5-0.6.
4. The semiconductor structure of claim 1, wherein a width of the first word line isolation structure along the second direction is equal to a width of the word line layer along the second direction, and wherein a width of the second word line isolation structure along the second direction is equal to a width of the stacked sub-structure along the second direction.
5. The semiconductor structure of claim 1, wherein a width of the first word line isolation structure along the first direction is equal to a pitch of adjacent word line layers along the first direction, and a width of the second word line isolation structure along the first direction is equal to a pitch of adjacent stacked sub-structures along the first direction.
6. A method of fabricating a semiconductor structure, comprising: Forming a plurality of stacked substructures on a substrate, wherein the stacked substructures are arranged along a first direction and comprise active layers and first dielectric layers which are alternately stacked along a vertical direction; forming a sacrificial structure between the stacked sub-structures; Forming a word line material layer and a first word line isolation structure, wherein the word line material layer is positioned on the top surface of the stacked sub-structures, the side wall perpendicular to the first direction and part of the surface of the sacrificial structure, and the first word line isolation structure is positioned between the stacked sub-structures; removing the sacrificial structure to form a communication groove; Removing part of the word line material layer exposed by the communication groove to form a word line layer, wherein the word line layer is positioned on the top surface of the stacked substructure and the side wall perpendicular to the first direction, and the bottom end of the word line layer is lower than the bottom surface of the stacked substructure; The second word line isolation structure is formed to fill the communication groove, the second word line isolation structure comprises a first isolation part, a second isolation part and a third isolation part which are sequentially connected, the first isolation part and the third isolation part extend along the vertical direction, the second isolation part extends along the second direction and is connected with the bottoms of the first isolation part and the third isolation part, and the bottom of the word line layer is connected with the top of the second isolation part.
7. The method of manufacturing of claim 6, wherein forming a stacked sub-structure on a substrate comprises: forming a stacked structure on a substrate, wherein the stacked structure comprises a first semiconductor layer and a second semiconductor layer which are alternately stacked; Removing a portion of the stacked structure and the substrate to form a plurality of first through holes and a patterned stacked structure, wherein the plurality of first through holes are arranged along a first direction and penetrate through the stacked structure, and the patterned stacked structure is positioned between the first through holes; Etching transversely along the first through holes, and removing part of the first semiconductor layer to form first clearance grooves, wherein the first clearance grooves are communicated with a plurality of first through holes; And depositing a first dielectric layer to form a stacked substructure, wherein the first dielectric layer fills the first clearance groove and covers the side walls of the plurality of first through holes.
8. The method of manufacturing of claim 7, wherein forming a sacrificial structure between the stacked sub-structures comprises: Forming a vertical sacrificial part filling a plurality of first through holes; And removing part of the vertical sacrificial part to form a sacrificial structure, wherein the sacrificial structure comprises a first sacrificial part, a second sacrificial part and a third sacrificial part which are sequentially connected, the first sacrificial part and the third sacrificial part extend along the vertical direction, the second sacrificial part extends along the second direction and is connected with the bottoms of the first sacrificial part and the third sacrificial part, and the top surface of the second sacrificial part is lower than the bottom surface of the stacked substructure.
9. The method of manufacturing of claim 8, wherein the first sacrificial portion, the second sacrificial portion, and the third sacrificial portion enclose a wordline trench, forming a wordline material layer and a first wordline isolation structure, comprising: removing the first dielectric layer exposed by the word line trench and located at the side wall part of the first through hole, Forming a gate dielectric layer on the side wall of the active layer exposed by the word line groove; and forming a word line material layer which conformally covers the inner wall of the word line groove and filling the first word line isolation structure.
10. The method of manufacturing of claim 8, wherein removing the sacrificial structure comprises: performing planarization treatment to expose top surfaces of the first sacrificial portion and the third sacrificial portion; and removing the first sacrificial part, the second sacrificial part and the third sacrificial part by adopting a wet etching process.

Description

Semiconductor structure and preparation method thereof Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. Background The development of dynamic memories (DRAMs) pursues performance indexes such as high speed, high integration density, low power consumption, etc., and with the miniaturization of the structure size of semiconductor devices, the technical barriers encountered by the existing structures are more and more obvious. Therefore, developing more novel structures based on existing structures is an advantageous means to break the prior art barriers. The advent of three-dimensional dynamic random access memory (3D DRAM), particularly 3D DRAM comprising multiple layers of horizontal memory cells (Multilayer Horizontal Cell, MHC), generally includes multiple transistors stacked on a substrate, meeting the above-mentioned needs. However, in the formation of vertical conductive lines (e.g., word lines) of a three-dimensional dynamic random access memory, a conductive line short problem due to conductive material residue is liable to occur due to the limitation of a dry etching process, resulting in a reduced memory reliability. Disclosure of Invention According to the first aspect of the embodiment of the disclosure, a semiconductor structure is provided, and the semiconductor structure is characterized by comprising a plurality of stacked substructures located on a substrate, wherein the stacked substructures are arranged at intervals along a first direction, each stacked substructure comprises an active layer and a first dielectric layer which are alternately stacked along a vertical direction, a word line layer is located on the top surface of the stacked substructures and is perpendicular to the side wall of the first direction, the bottom end of the word line layer is lower than the bottom surface of the stacked substructures, a first word line isolation structure is located between the stacked substructures, a second word line isolation structure comprises a first isolation part, a second isolation part and a third isolation part which are sequentially connected, the first isolation part and the third isolation part extend along the vertical direction, the second isolation part extends along a second direction and is connected with the bottom of the first isolation part and the third isolation part, and the bottom end of the word line layer is connected with the top of the second isolation part. In some embodiments, the substrate includes protrusions under the stacked substructure, the second spacers are located between the protrusions, and the top surfaces of the second spacers are lower than the top surfaces of the protrusions. In some embodiments, the semiconductor device further comprises a gate dielectric layer, a substrate protection layer and a substrate protection layer, wherein the gate dielectric layer covers the side wall of the active layer perpendicular to the first direction, the substrate protection layer covers the side wall and the bottom of a groove formed between adjacent protruding parts, the substrate protection layer is arranged between the second isolation part and the substrate in a clamping mode, the thickness of the substrate protection layer is larger than that of the gate dielectric layer, and the ratio of the thickness of the substrate protection layer to that of the first dielectric layer is in the range of 0.5-0.6. In some embodiments, the width of the first word line isolation structure in the second direction is equal to the width of the word line layer in the second direction, and the width of the second word line isolation structure in the second direction is equal to the width of the stacked sub-structure in the second direction. In some embodiments, the width of the first word line isolation structure along the first direction is equal to the pitch of adjacent word line layers along the first direction, and the width of the second word line isolation structure along the first direction is equal to the pitch of adjacent stacked sub-structures along the first direction. According to a second aspect of the embodiment of the disclosure, a preparation method of a semiconductor structure is provided, wherein the preparation method comprises the steps of forming a plurality of stacked sub-structures on a substrate, the stacked sub-structures are arranged along a first direction, the stacked sub-structures comprise active layers and first dielectric layers which are alternately stacked along a vertical direction, forming sacrificial structures between the stacked sub-structures, forming word line material layers and first word line isolation structures, the word line material layers are located on the top surfaces of the stacked sub-structures, side walls perpendicular to the first direction and part surfaces of the sacrificial structures, the first