CN-122002787-A - Semiconductor device, preparation method thereof and memory system

Abstract

The embodiment of the disclosure provides a semiconductor device, a preparation method thereof and a memory system. The semiconductor device includes a word line structure, a first channel structure, and a second channel structure. The first channel structure extends in a first direction. The second channel structure extends along the first direction, wherein the first channel structure and the second channel structure have a separation distance in the second direction. The word line structure extends in a second direction, and the first channel structure and the second channel structure are located on opposite sides of the word line structure in a third direction. The first direction, the second direction, and the third direction intersect each other.

Inventors

• LIU ZICHEN
• LIU WEI
• HUO ZONGLIANG

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260508

Application Date

20241105

Claims (20)

1. 1. A semiconductor device, comprising: a word line structure; a first channel structure extending in a first direction; A second channel structure extending along the first direction, wherein the first channel structure and the second channel structure have a spacing distance in a second direction, and Wherein the word line structure extends along the second direction, the first channel structure and the second channel structure being located on opposite sides of the word line structure in a third direction; the first direction, the second direction, and the third direction intersect each other.
2. 2. The semiconductor device of claim 1, wherein in the third direction, the first channel structure and the second channel structure have one of the word line structures therebetween.
3. 3. The semiconductor device of claim 1, further comprising: A first bit line structure located at one side of the first channel structure in the first direction and extending along the third direction, and A second bit line structure located at one side of the second channel structure in the first direction and extending along the third direction; The first bit line structure is connected with the first channel structure, and the second bit line structure is connected with the second channel structure.
4. 4. The semiconductor device of claim 3, wherein the second direction is perpendicular to the third direction.
5. 5. The semiconductor device of claim 4, wherein a plurality of the first channel structures and a plurality of the second channel structures are alternately arranged in the second direction, and a plurality of the first bit line structures and a plurality of the second bit line structures are alternately arranged in the second direction.
6. 6. The semiconductor device of claim 5, wherein the plurality of first channel structures and the plurality of second channel structures are arranged equidistant in the second direction, the plurality of first bit line structures and the plurality of second bit line structures are arranged equidistant, and the plurality of word line structures are arranged equidistant in the third direction.
7. 7. The semiconductor device according to claim 3, further comprising: A first capacitor located at one side of the first channel structure facing away from the first bit line structure and connected with the first channel structure, and And the second capacitor is positioned on one side of the second channel structure, which is away from the second bit line structure, and is connected with the second channel structure.
8. 8. The semiconductor device of claim 7, wherein, The first capacitor includes a first conductive portion extending along the first direction, the first conductive portion being in contact with the first channel structure; the second capacitor includes a second conductive portion extending along the first direction, the second conductive portion being in contact with the second channel structure.
9. 9. The semiconductor device of claim 8, wherein in the first direction, the first conductive portion is aligned with the first channel structure and the second conductive portion is aligned with the second channel structure.
10. 10. The semiconductor device according to claim 8, wherein the first conductive portion and the second conductive portion have a separation distance in the second direction.
11. 11. The semiconductor device of claim 8, wherein the first capacitor and the second capacitor further comprise: An insulating layer covering at least part of the first conductive portion and at least part of the second conductive portion, and And a conductive layer covering the insulating layer.
12. 12. The semiconductor device according to claim 3, wherein, The first channel structure comprises a first main body part, a first extension part and a second extension part, the first main body part extends along the first direction, the first extension part is positioned at the end part of the first main body part, which is close to the first bit line structure, and the second extension part is positioned at the end part of the first main body part, which is away from the first bit line structure, wherein the extension directions of the first extension part and the second extension part are opposite in the third direction; the second channel structure comprises a second main body part, a third extension part and a fourth extension part, wherein the second main body part extends along the first direction, the third extension part is positioned at the end part of the second main body part, which is close to the second bit line structure, and the fourth extension part is positioned at the end part of the second main body part, which is away from the second bit line structure, wherein in the third direction, the extension directions of the third extension part and the fourth extension part are opposite.
13. 13. The semiconductor device of claim 12, wherein, The first body portion has a dimension in the second direction that is greater than a dimension of the first body portion in the third direction; the second body portion has a dimension in the second direction that is greater than a dimension of the second body portion in the third direction.
14. 14. The semiconductor device according to claim 12, wherein the first extension and the third extension are opposite in extending direction, and the second extension and the fourth extension are opposite in extending direction.
15. 15. The semiconductor device of claim 1, wherein the material of the first channel structure and the second channel structure comprises a metal oxide semiconductor.
16. 16. The semiconductor device of claim 15, wherein the metal oxide semiconductor comprises indium gallium zinc oxide.
17. 17. The semiconductor device of claim 3, wherein a dimension of an end of the word line structure adjacent to the first bit line structure in the third direction is less than a dimension of an end of the word line structure facing away from the first bit line structure in the third direction.
18. 18. The semiconductor device of claim 1, further comprising: a first dielectric layer between the first channel structure and the word line structure, and And the second dielectric layer is positioned between the second channel structure and the word line structure.
19. 19. A memory system, comprising: A memory comprising the semiconductor device according to any one of claims 1 to 18, and And the controller is coupled with the memory and used for controlling the memory to store data.
20. 20. A method of fabricating a semiconductor device, comprising: Forming a word line structure; Forming a first channel structure extending along a first direction and a second channel structure extending along the first direction; Wherein the word line structure extends in a second direction, the first channel structure and the second channel structure are located on opposite sides of the word line structure in a third direction, the first channel structure and the second channel structure have a separation distance in the second direction, and the first direction, the second direction, and the third direction intersect each other.

Description

Semiconductor device, preparation method thereof and memory system Technical Field The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a memory system, and a method of manufacturing the semiconductor device. Background The semiconductor device may include a memory for implementing a data storage function, such as a dynamic random access memory (Dynamic Random Access Memory, DRAM). DRAM is widely used in the memory of electronic devices such as computers and mobile phones due to its simple structure, large capacity, high density, low power consumption, and high speed. Semiconductor devices are expected to have higher storage densities, more excellent electrical properties, and simpler fabrication processes. Disclosure of Invention In a first aspect, some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a word line structure, a first channel structure, and a second channel structure. The first channel structure extends in a first direction. The second channel structure extends along the first direction, wherein the first channel structure and the second channel structure have a separation distance in the second direction. The word line structure extends in a second direction, and the first channel structure and the second channel structure are located on opposite sides of the word line structure in a third direction. The first direction, the second direction, and the third direction intersect each other. For example, the second direction is perpendicular to the third direction. In an exemplary embodiment, in the third direction, there is one word line structure between the first channel structure and the second channel structure. In an exemplary embodiment, the semiconductor device may further include a first bit line structure and a second bit line structure. The first bit line structure is located at one side of the first channel structure in the first direction and extends along the third direction. The second bit line structure is located at one side of the second channel structure in the first direction and extends along the third direction. The first bit line structure is connected with the first channel structure, and the second bit line structure is connected with the second channel structure. In an exemplary embodiment, the plurality of first channel structures and the plurality of second channel structures are alternately arranged in the second direction, and the plurality of first bit line structures and the plurality of second bit line structures are alternately arranged in the second direction. In an exemplary embodiment, the plurality of first channel structures and the plurality of second channel structures are arranged equidistantly in the second direction, the plurality of first bit line structures and the plurality of second bit line structures are arranged equidistantly, and the plurality of word line structures are arranged equidistantly in the third direction. In an exemplary embodiment, the semiconductor device further includes a first capacitor and a second capacitor. The first capacitor is located on one side of the first channel structure away from the first bit line structure and is connected with the first channel structure. The second capacitor is positioned on one side of the second channel structure away from the second bit line structure and is connected with the second channel structure. In an exemplary embodiment, the first capacitor includes a first conductive portion extending in a first direction, the first conductive portion being in contact with the first channel structure, and the second capacitor includes a second conductive portion extending in the first direction, the second conductive portion being in contact with the second channel structure. In an exemplary embodiment, in a first direction, the first conductive portion is aligned with the first channel structure and the second conductive portion is aligned with the second channel structure. In an exemplary embodiment, the first conductive portion and the second conductive portion have a separation distance in the second direction. In an exemplary embodiment, the first capacitor and the second capacitor further include an insulating layer and a conductive layer. The insulating layer covers at least part of the first conductive portion and at least part of the second conductive portion, and the conductive layer covers the insulating layer. In an exemplary embodiment, the first channel structure includes a first body portion extending in a first direction, a first extension portion located at an end of the first body portion near the first bit line structure, and a second extension portion located at an end of the first body portion facing away from the first bit line structure, wherein in a third direction, the extending directions of the first extension portion and the second extension portio